From: lkcl <lkcl@web>
Date: Fri, 3 Jun 2022 14:09:15 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1997
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=291da4fef335742cd9e1721da68d0b20ba1d9ea6;p=libreriscv.git

---

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index bbc3e4620..b4618ad1e 100644
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -124,7 +124,7 @@ to a *CR Field* (CR0-CR7) and consequently these operands
 (BF, BFA etc) are only 3-bits.
 
 With SVP64 extending the number of CR *Fields* to 128, the number of
-CR *Registers* extends to 16, in order to hold all 128 CR *Fields*
+32-bit CR *Registers* extends to 16, in order to hold all 128 CR *Fields*
 (8 per CR Register). Then, it gets even more strange, when it comes
 to Vectorisation, which applies to the CR *Field* numbers.  The
 hardware-for-loop for Rc=1 for example starts at CR0 for element 0,