From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 23 Dec 2021 17:05:53 +0000 (+0000)
Subject: allow MSR reset to default to a value set by issuer_verilog.py
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=292cc4f8c58404dd842f39ddd3cf18c9d56cf95d;p=soc.git

allow MSR reset to default to a value set by issuer_verilog.py
---

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index 28f8172d..df2fd4a8 100644
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -70,8 +70,8 @@ class StateRegs(RegFileArray, StateRegsEnum):
     (d_rd2)
 
     """
-    def __init__(self, svp64_en=False, regreduce_en=False):
-        super().__init__(64, StateRegsEnum.N_REGS)
+    def __init__(self, svp64_en=False, regreduce_en=False, resets=None):
+        super().__init__(64, StateRegsEnum.N_REGS, resets=resets)
         wr_spec, rd_spec = self.get_port_specs()
         create_ports(self, wr_spec, rd_spec)
 
@@ -255,7 +255,8 @@ class RegFiles:
               ('fast', FastRegs),
               ('state', StateRegs),
               ('spr', SPRRegs),]
-    def __init__(self, pspec, make_hazard_vecs=False):
+    def __init__(self, pspec, make_hazard_vecs=False,
+                      state_resets=None): # state file reset values
         # test is SVP64 is to be enabled
         svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
 
@@ -266,7 +267,10 @@ class RegFiles:
         self.rf = {} # register file dict
         # create regfiles here, Factory style
         for (name, kls) in RegFiles.regkls:
-            rf = self.rf[name] = kls(svp64_en, regreduce_en)
+            kwargs = {'svp64_en': svp64_en, 'regreduce_en': regreduce_en}
+            if name == 'state':
+                kwargs['resets'] = state_resets
+            rf = self.rf[name] = kls(**kwargs)
             # also add these as instances, self.state, self.fast, self.cr etc.
             setattr(self, name, rf)
 
diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index bc2d0fbf..718b983f 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -159,8 +159,16 @@ class NonProductionCore(ControlBase):
             # urr store I-Cache in core so it is easier to get at
             self.icache = lsi.icache
 
+        self.msr_at_reset = 0x0
+        if hasattr(pspec, "msr_reset") and isinstance(pspec.msr_reset, int):
+            self.msr_at_reset = pspec.msr_reset
+        state_resets = [0x0,               # PC at reset
+                        self.msr_at_reset, # MSR at reset
+                        0x0]               # SVSTATE at reset
+
         # register files (yes plural)
-        self.regs = RegFiles(pspec, make_hazard_vecs=self.make_hazard_vecs)
+        self.regs = RegFiles(pspec, make_hazard_vecs=self.make_hazard_vecs,
+                                    state_resets=state_resets)
 
         # set up input and output: unusual requirement to set data directly
         # (due to the way that the core is set up in a different domain,