From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Wed, 20 May 2015 20:49:01 +0000 (-0700)
Subject: Take interrupts as soon as interrupts are enabled
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=292fef830dad9d6d8b868ba27cf4ddd80bf9243a;p=riscv-isa-sim.git

Take interrupts as soon as interrupts are enabled

Previously, if interrupts were enabled then disabled quickly enough,
no interrupt would ever be taken, resulting in deadlock.
---

diff --git a/riscv/insns/c_addi4.h b/riscv/insns/c_addi4.h
deleted file mode 100644
index 3c9b7b2..0000000
--- a/riscv/insns/c_addi4.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_extension('C');
-WRITE_RD(sext_xlen(RVC_RS2 + insn.rvc_lwsp_imm()));
diff --git a/riscv/insns/c_jalr.h b/riscv/insns/c_jalr.h
deleted file mode 100644
index ef6edfc..0000000
--- a/riscv/insns/c_jalr.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_extension('C');
-reg_t tmp = npc;
-set_pc(RVC_RS1 & ~reg_t(1));
-WRITE_RD(tmp);
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 2978ef8..b8e848b 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -230,7 +230,7 @@ void processor_t::step(size_t n)
    if (unlikely(pc == PC_SERIALIZE)) { \
      pc = state.pc; \
      state.serialized = true; \
-     continue; \
+     break; \
    }
 
   try
@@ -276,7 +276,7 @@ void processor_t::step(size_t n)
   }
   catch(trap_t& t)
   {
-    state.pc = take_trap(t, pc);
+    take_trap(t, pc);
   }
 
   update_timer(&state, instret);
@@ -307,19 +307,18 @@ void processor_t::pop_privilege_stack()
   set_csr(CSR_MSTATUS, s);
 }
 
-reg_t processor_t::take_trap(trap_t& t, reg_t epc)
+void processor_t::take_trap(trap_t& t, reg_t epc)
 {
   if (debug)
     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
             id, t.name(), epc);
 
-  reg_t tvec = DEFAULT_MTVEC + 0x40 * get_field(state.mstatus, MSTATUS_PRV);
+  state.pc = DEFAULT_MTVEC + 0x40 * get_field(state.mstatus, MSTATUS_PRV);
   push_privilege_stack();
   yield_load_reservation();
   state.mcause = t.cause();
   state.mepc = epc;
   t.side_effects(&state); // might set badvaddr etc.
-  return tvec;
 }
 
 void processor_t::deliver_ipi()
diff --git a/riscv/processor.h b/riscv/processor.h
index 61d77cb..1d497d0 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -119,7 +119,7 @@ private:
   std::map<size_t,size_t> pc_histogram;
 
   void take_interrupt(); // take a trap if any interrupts are pending
-  reg_t take_trap(trap_t& t, reg_t epc); // take an exception
+  void take_trap(trap_t& t, reg_t epc); // take an exception
   void disasm(insn_t insn); // disassemble and print an instruction
 
   friend class sim_t;