From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Fri, 17 Jul 2020 15:20:53 +0000 (+0200)
Subject: Fix PHY issues
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=293495ed65d1ec17bd4203b4a1de1c1257fb6ab7;p=gram.git

Fix PHY issues
---

diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py
index e5394b5..db692f8 100644
--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -254,7 +254,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
             with m.Switch(dqs_bitslip):
                 for j, b in enumerate(range(-2, 2)):
                     with m.Case(j):
-                        m.d.sync += dqs_read.eq(rddata_en[cl_sys_latency + b:cl_sys_latency + b + 2] != 0)
+                        m.d.sync += dqs_read.eq(1)
 
             m.submodules += Instance("DQSBUFM",
                                      p_DQS_LI_DEL_ADJ="MINUS",
@@ -450,7 +450,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
                 ]
                 m.d.sync += dq_i_data[:4].eq(dq_i_data[4:])
                 m.d.sync += dq_i_data[4:].eq(_dq_i_data)
-                m.d.comb += [
+                m.d.sync += [
                     dfi.phases[0].rddata[0*databits+j].eq(dq_i_data[0]),
                     dfi.phases[0].rddata[1*databits+j].eq(dq_i_data[1]),
                     dfi.phases[0].rddata[2*databits+j].eq(dq_i_data[2]),