From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 27 May 2020 07:00:43 +0000 (+0200)
Subject: CHANGES: add JTAG UART.
X-Git-Tag: 24jan2021_ls180~287
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2934c085ef27838d5589ced44af4c9b199b4c9bf;p=litex.git

CHANGES: add JTAG UART.
---

diff --git a/CHANGES b/CHANGES
index 1755643a..e676f2cf 100644
--- a/CHANGES
+++ b/CHANGES
@@ -7,6 +7,7 @@
 
 	[> Added Features
 	------------------
+	- JTAG UART with uart_name=jtag_uart (validated on Spartan6, 7-Series, Ultrascale(+)).
 	- Add CV32E40P CPU support (ex RI5CY).
 	- Use InterconnectPointToPoint when 1 master,1 slave and no address translation.
 	- Improve WishboneBridge.