From: Sebastien Bourdeauducq Date: Thu, 29 Nov 2012 22:41:51 +0000 (+0100) Subject: Replace Signal(bits_for(... with Signal(max=... X-Git-Tag: 24jan2021_ls180~3069 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=293a62dabefa4d74030adfb1a00226b96e4c1abe;p=litex.git Replace Signal(bits_for(... with Signal(max=... --- diff --git a/milkymist/asmicon/bankmachine.py b/milkymist/asmicon/bankmachine.py index 1fe39f4d..8b174081 100644 --- a/milkymist/asmicon/bankmachine.py +++ b/milkymist/asmicon/bankmachine.py @@ -42,7 +42,7 @@ class _Selector: self.nslots = len(self.slots) self.stb = Signal() self.ack = Signal() - self.tag = Signal(bits_for(self.nslots-1)) + self.tag = Signal(max=self.nslots) self.adr = Signal(self.slots[0].adr.nbits) self.we = Signal() @@ -238,7 +238,7 @@ class BankMachine: # Respect write-to-precharge specification precharge_ok = Signal() t_unsafe_precharge = 2 + self.timing_settings.tWR - 1 - unsafe_precharge_count = Signal(bits_for(t_unsafe_precharge)) + unsafe_precharge_count = Signal(max=t_unsafe_precharge+1) comb.append(precharge_ok.eq(unsafe_precharge_count == 0)) sync += [ If(self.cmd.stb & self.cmd.ack & self.cmd.is_write, diff --git a/milkymist/asmicon/multiplexer.py b/milkymist/asmicon/multiplexer.py index 7c174584..6258e6b0 100644 --- a/milkymist/asmicon/multiplexer.py +++ b/milkymist/asmicon/multiplexer.py @@ -64,7 +64,7 @@ class _Steerer: ncmd = len(self.commands) nph = len(self.dfi.phases) - self.sel = [Signal(bits_for(ncmd-1)) for i in range(nph)] + self.sel = [Signal(max=ncmd) for i in range(nph)] def get_fragment(self): comb = [] @@ -194,7 +194,7 @@ class Multiplexer: max_time = Signal() if timeout: t = timeout - 1 - time = Signal(bits_for(t)) + time = Signal(max=t+1) comb.append(max_time.eq(time == 0)) sync.append( If(~en, diff --git a/milkymist/asmicon/refresher.py b/milkymist/asmicon/refresher.py index ccab764e..463f673a 100644 --- a/milkymist/asmicon/refresher.py +++ b/milkymist/asmicon/refresher.py @@ -45,7 +45,7 @@ class Refresher: ]) # Periodic refresh counter - counter = Signal(bits_for(self.tREFI - 1)) + counter = Signal(max=self.tREFI) start = Signal() sync += [ start.eq(0),