From: lkcl <lkcl@web>
Date: Fri, 19 Aug 2022 05:42:53 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~830
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=29498664bacbc1ed70e63f884fa501528063836a;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 784a068fd..62e6a2c2d 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -9,6 +9,7 @@ Links:
 * <https://bugs.libre-soc.org/show_bug.cgi?id=571>
 * <https://llvm.org/devmtg/2016-11/Slides/Emerson-ScalableVectorizationinLLVMIR.pdf>
 * <https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-loads-and-stores>
+* [[ldst/discussion]]
 
 # Rationale
 
@@ -502,61 +503,3 @@ LD/ST, will give that same capability, with far more flexibility.
 Also LD/ST with immediate has a Pack/Unpack option similar to VSX
 'vpack' and 'vunpack'.
 
-# notes from lxo
-
-this section covers assembly notation for the immediate and indexed LD/ST.
-the summary is that in immediate mode for LD it is not clear that if the 
-destination register is Vectorised `RT.v` but the source `imm(RA)` is scalar
-the memory being read is *still a vector load*, known as "unit or element strides".
-
-This anomaly is made clear with the following notation:
-
-    sv.ld RT.v, imm(RA).v
-
-The following notation, although technically correct due to being implicitly identical to the above, is prohibited and is a syntax error:
- 
-    sv.ld RT.v, imm(RA)
-
-Notes taken from IRC conversation
-
-    <lxo> sv.ld r#.v, ofst(r#).v -> the whole vector is at ofst+r#
-    <lxo> sv.ld r#.v, ofst(r#.v) -> r# is a vector of addresses
-    <lxo> similarly sv.ldx r#.v, r#, r#.v -> whole vector at r#+r#
-    <lxo> whereas sv.ldx r#.v, r#.v, r# -> vector of addresses
-    <lxo> point being, you take an operand with the "m" constraint (or other memory-operand constraints), append .v to it and you're done addressing the in-memory vector
-    <lxo> as in asm ("sv.ld1 %0.v, %1.v" : "=r"(vec_in_reg) : "m"(vec_in_mem));
-    <lxo> (and ld%U1 got mangled into underline; %U expands to x if the address is a sum of registers
-
-permutations of vector selection, to identify above asm-syntax:
-
-     imm(RA)  RT.v   RA.v   nonstrided
-         sv.ld r#.v, ofst(r#2.v) -> r#2 is a vector of addresses
-           mem@     0+r#2   offs+(r#2+1)  offs+(r#2+2)
-           destreg  r#      r#+1          r#+2
-     imm(RA)  RT.s   RA.v   nonstrided
-         sv.ld r#, ofst(r#2.v) -> r#2 is a vector of addresses
-           (dest r# is scalar) -> VSELECT mode
-     imm(RA)  RT.v   RA.s   fixed stride: unit or element
-         sv.ld r#.v, ofst(r#2).v -> whole vector is at ofst+r#2
-           mem@r#2  +0   +1   +2
-           destreg  r#   r#+1 r#+2
-         sv.ld/els r#.v, ofst(r#2).v -> vector at ofst*elidx+r#2
-           mem@r#2  +0 ...   +offs ...  +offs*2
-           destreg  r#       r#+1       r#+2
-     imm(RA)  RT.s   RA.s   not vectorised
-         sv.ld r#, ofst(r#2)
-
-indexed mode:
-
-     RA,RB    RT.v  RA.v  RB.v
-        sv.ldx r#.v, r#2, r#3.v -> whole vector at r#2+r#3
-     RA,RB    RT.v  RA.s  RB.v
-        sv.ldx r#.v, r#2.v, r#3.v -> whole vector at r#2+r#3
-     RA,RB    RT.v  RA.v  RB.s
-        sv.ldx r#.v, r#2.v, r#3 -> vector of addresses
-     RA,RB    RT.v  RA.s  RB.s
-        sv.ldx r#.v, r#2, r#3 -> VSPLAT mode
-     RA,RB    RT.s  RA.v  RB.v
-     RA,RB    RT.s  RA.s  RB.v
-     RA,RB    RT.s  RA.v  RB.s
-     RA,RB    RT.s  RA.s  RB.s not vectorised