From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 15 Jun 2019 16:08:56 +0000 (-0700)
Subject: Wrap FDRE with $__ABC_FDRE containing comb
X-Git-Tag: working-ls180~881^2^2~319
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=295bb23ae06d36acc8ced4825ece6003470cd357;p=yosys.git

Wrap FDRE with $__ABC_FDRE containing comb
---

diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index 1a652eb27..12ec20053 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -30,6 +30,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_ff.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut))
 
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 8a48bad4e..653f6bcb3 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -41,10 +41,10 @@ RAM128X1D 5 0 17 2
 -   -   -   -   -   -   -   - 314 314 314 314 314 314 292 - -
 347 347 347 347 347 347 296 - -   -   -   -   -   -   -   - -
 
-# Inputs: C CE D R
-# Outputs: Q
-FDRE 6 0 4 1
-- - - -
+# Inputs: C CE D R Q_past
+# Outputs: Q_next
+FDRE 6 1 5 1
+- - - - -
 
 # Inputs: C CE D S
 # Outputs: Q
diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v
index 13beaa6ae..ba34425d6 100644
--- a/techlibs/xilinx/ff_map.v
+++ b/techlibs/xilinx/ff_map.v
@@ -23,7 +23,15 @@
 `ifndef _NO_FFS
 
 module  \$_DFF_N_   (input D, C, output Q);    FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
-module  \$_DFF_P_   (input D, C, output Q);    FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
+module  \$_DFF_P_   (input D, C, output Q);
+`ifndef _ABC
+	FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
+`else
+    wire Q_next;
+	\$__ABC_FDRE #(/*.INIT(|0)*/) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(1'b1), .R(1'b0));
+	\$_DFF_P_ abc_dff (.D(Q_next), .Q(Q), .C(C));
+`endif
+endmodule
 
 module  \$_DFFE_NP_ (input D, C, E, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0)); endmodule
 module  \$_DFFE_PP_ (input D, C, E, output Q); FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0)); endmodule
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index a11648873..b9da4e6a6 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -276,25 +276,33 @@ struct SynthXilinxPass : public ScriptPass
 
 		if (check_label("map_cells")) {
 			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
+			if (abc == "abc9")
+				run("techmap -max_iter 1 -D _ABC -map +/xilinx/ff_map.v");
 			run("clean");
 		}
 
 		if (check_label("map_luts")) {
-			if (abc == "abc9")
-				run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -dff" : ""));
-			else if (help_mode)
+			if (abc == "abc9") {
+				run("read_verilog -icells -lib +/xilinx/abc_ff.v");
+				run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -retime" : ""));
+			}
+			else if (help_mode) {
 				run(abc + " -luts 2:2,3,6:5,10,20 [-dff]");
-			else
+				run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+						"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
+			}
+			else {
 				run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
+				run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+						"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
+			}
 			run("clean");
 
 			// This shregmap call infers fixed length shift registers after abc
 			//   has performed any necessary retiming
 			if (!nosrl || help_mode)
 				run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
-			run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
-			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
+			run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v");
 			run("clean");
 		}