From: lkcl <lkcl@web>
Date: Sun, 14 Nov 2021 09:56:50 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~3427
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=29713fd77f142b664131a10a12d0e7cf8947c8ba;p=libreriscv.git

---

diff --git a/docs/pinmux.mdwn b/docs/pinmux.mdwn
index 78b54153a..12b813857 100644
--- a/docs/pinmux.mdwn
+++ b/docs/pinmux.mdwn
@@ -24,7 +24,11 @@ absolutely out of the question.
 Yet, the expectation from the market is to be able to fit 1,000++
 pins worth of peripherals into only 200 to 400 worth of actual
 IO Pads. The solution here: a GPIO Pinmux, described in some
-detail here 
+detail here <https://ftp.libre-soc.org/Pin_Control_Subsystem_Overview.pdf>
+
+This page goes over the details and issues involved in creating
+an ASIC that combines **both** JTAG Boundary Scan **and** GPIO
+Muxing, down to layout considerations using coriolis2.
 
 <img src="https://libre-soc.org/shakti/m_class/JTAG/jtag-block.jpg"
   width=600 />