From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 30 Aug 2019 22:00:40 +0000 (-0700)
Subject: Update comment
X-Git-Tag: working-ls180~1039^2~224
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2983a35dc058a5f5a1ab7b23cc55dd6f83667d88;p=yosys.git

Update comment
---

diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 24bdfd3f2..8221cdb69 100644
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -89,11 +89,11 @@ code sigB clock clock_pol
 endcode
 
 match ffFJKG
+	// Ensure pipeline register is not already used
 	if mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())
 	select ffFJKG->type.in($dff)
 	select nusers(port(ffFJKG, \D)) == 2
 	index <SigSpec> port(ffFJKG, \D) === sigH
-	// Ensure pipeline register is not already used
 	optional
 endmatch