From: Marek Olšák <marek.olsak@amd.com>
Date: Wed, 28 Mar 2018 01:19:15 +0000 (-0400)
Subject: radeonsi: don't flush HTILE if there is no HTILE clear
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=29a09e1d380375bd3483d52ac5efdc8b47cc9851;p=mesa.git

radeonsi: don't flush HTILE if there is no HTILE clear

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
---

diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index f8136d2b2c4..4e05d9bf5b2 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -593,9 +593,9 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
 		 *
 		 * This hack decreases back-to-back ClearDepth performance.
 		 */
-		if (sctx->screen->clear_db_cache_before_clear) {
+		if ((sctx->db_depth_clear || sctx->db_stencil_clear) &&
+		    sctx->screen->clear_db_cache_before_clear)
 			sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
-		}
 	}
 
 	si_blitter_begin(sctx, SI_CLEAR);