From: whitequark <whitequark@whitequark.org>
Date: Fri, 12 Jun 2020 00:05:05 +0000 (+0000)
Subject: cxxrtl: unbuffer output wires of toplevel module.
X-Git-Tag: working-ls180~478^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=29bd81d66239b22ffdbe1f72416624823d712d34;p=yosys.git

cxxrtl: unbuffer output wires of toplevel module.

Without unbuffering output wires of, at least, toplevel modules, it
is not possible to have most designs that rely on IO via toplevel
ports (as opposed to using exclusively blackboxes) converge within
one delta cycle. That seriously impairs the performance of CXXRTL.

This commit avoids unbuffering outputs of all modules solely so that
in future, CXXRTL could gain fully separate compilation, and not for
any present technical reason.
---

diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index 0a810b8d1..c6b8bbc47 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -2154,7 +2154,7 @@ struct CxxrtlWorker {
 
 			for (auto wire : module->wires()) {
 				if (feedback_wires[wire]) continue;
-				if (wire->port_output) continue;
+				if (wire->port_output && !module->get_bool_attribute(ID::top)) continue;
 				if (wire->name.begins_with("$") && !unbuffer_internal) continue;
 				if (wire->name.begins_with("\\") && !unbuffer_public) continue;
 				if (flow.wire_sync_defs.count(wire) > 0) continue;