From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 12 Jul 2018 01:03:00 +0000 (+0100)
Subject: add memory slide
X-Git-Tag: convert-csv-opcode-to-binary~5067
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=29c185603ccef66edde5be511a8d129983f17a8d;p=libreriscv.git

add memory slide
---

diff --git a/shakti/m_class/HyperRAM.mdwn b/shakti/m_class/HyperRAM.mdwn
index 58f9fb46e..f0a2648b7 100644
--- a/shakti/m_class/HyperRAM.mdwn
+++ b/shakti/m_class/HyperRAM.mdwn
@@ -1,4 +1,5 @@
 # HyperRAM (Octal SPI)
 
 * <https://github.com/blackmesalabs/hyperram>
-
+* Symbiotic EDA have a DDR variant that they can make libre for the
+  right $
diff --git a/shakti/m_class/libre_riscv_chennai_2018.tex b/shakti/m_class/libre_riscv_chennai_2018.tex
index 16573fde8..9453f1625 100644
--- a/shakti/m_class/libre_riscv_chennai_2018.tex
+++ b/shakti/m_class/libre_riscv_chennai_2018.tex
@@ -212,6 +212,28 @@
 }
 
 
+\frame{\frametitle{Challenging Stuff [1] - Memory Interfaces}
+
+ \begin{itemize}
+   \item DDR3/4 PHYs are analog and very high speed.
+		   Impedance training.  Extreme timing tolerances on parallel buses.\\
+		   No surprise they cost USD \$1m and above.
+   \item Symbiotic EDA will do (Libre) PHY layout for USD \$300k,
+	     time to completion for chosen geometry: 8-12 months.
+  \end{itemize}
+   {\it Silicon-proven but still risky.  What are the alternatives?}
+   \vspace{4pt}
+ \begin{itemize}
+   \item 133mhz 32-bit SDRAM (um...) maybe even FlexBus?
+   \item HyperRAM (aka JEDEC xSPI) 8-bit SPI 166mhz or DDR-300.\\
+	   300mbyte/sec for only 13 wires, not bad!  (We'll take several)\\
+	   http://libre-riscv.org/shakti/m\_class/HyperRAM/
+   \item HMC: insanely fast, very low power.  OpenHMC (LGPL)
+	   https://opencores.org/project/openhmc
+  \end{itemize}
+}
+
+
 \frame{\frametitle{TODO}
 
  \begin{itemize}