From: Dennis Zhang Date: Tue, 6 Oct 2020 15:53:46 +0000 (+0100) Subject: arm: Enable MVE SIMD modes for vectorization X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=29c650cd899496c4f9bc069d03d0d7ecfb632176;p=gcc.git arm: Enable MVE SIMD modes for vectorization This patch enables SIMD modes for MVE auto-vectorization. In this patch, the integer and float MVE SIMD modes are returned by arm_preferred_simd_mode (TARGET_VECTORIZE_PREFERRED_SIMD_MODE hook) when MVE or MVE_FLOAT is enabled. Then the expanders for auto-vectorization can be used for generating MVE SIMD code. This patch also fixes bugs in MVE vreiterpretq_*.c tests which are revealed by the enabled MVE SIMD modes. The tests are for checking the MVE reinterpret intrinsics. There are two functions in each of the tests. The two functions contain the pattern of identical code so that they are folded in icf pass. Because of icf, the instruction count only checks one function which is 8. However when the SIMD modes are enabled, the estimation of the code size becomes smaller so that inlining is applied after icf, then the instruction count becomes 16 which causes failure of the tests. Because the icf is not the expected pattern to be tested but causes above issues, -fno-ipa-icf is applied to the tests to avoid unstable instruction count. gcc/ChangeLog: 2020-10-05 Dennis Zhang * config/arm/arm.c (arm_preferred_simd_mode): Enable MVE SIMD modes. gcc/testsuite/ChangeLog: 2020-10-05 Dennis Zhang * gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c: Use additional option -fno-ipa-icf and change the instruction count from 8 to 16. * gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c: Likewise. --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index cd3901b940c..743e4978857 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2020-10-05 Dennis Zhang + + * config/arm/arm.c (arm_preferred_simd_mode): Enable MVE SIMD modes. + 2020-10-05 Aldy Hernandez * value-range.cc (irange::legacy_intersect): Only handle diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index bd7be8fde01..5fdc1439636 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -28964,6 +28964,30 @@ arm_preferred_simd_mode (scalar_mode mode) default:; } + if (TARGET_HAVE_MVE) + switch (mode) + { + case QImode: + return V16QImode; + case HImode: + return V8HImode; + case SImode: + return V4SImode; + + default:; + } + + if (TARGET_HAVE_MVE_FLOAT) + switch (mode) + { + case HFmode: + return V8HFmode; + case SFmode: + return V4SFmode; + + default:; + } + return word_mode; } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5b92a025a4b..703cc683fe7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,17 @@ +2020-10-05 Dennis Zhang + + * gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c: Use additional + option -fno-ipa-icf and change the instruction count from 8 to 16. + * gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c: Likewise. + * gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c: Likewise. + * gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c: Likewise. + 2020-10-05 Nathan Sidwell * c-c++-common/spellcheck-reserved.c: Restore diagnostic. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c index f59f69734ed..2398d894861 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c @@ -1,6 +1,6 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2 -fno-ipa-icf" } */ #include "arm_mve.h" int8x16_t value1; @@ -41,4 +41,4 @@ foo1 () return vaddq_f16 (r7, vreinterpretq_f16 (value9)); } -/* { dg-final { scan-assembler-times "vadd.f16" 8 } } */ +/* { dg-final { scan-assembler-times "vadd.f16" 16 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c index dac47c7e924..5a58dc6eb4c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c @@ -1,6 +1,6 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2 -fno-ipa-icf" } */ #include "arm_mve.h" int16x8_t value1; @@ -41,4 +41,4 @@ foo1 () return vaddq_f32 (r7, vreinterpretq_f32 (value9)); } -/* { dg-final { scan-assembler-times "vadd.f32" 8 } } */ +/* { dg-final { scan-assembler-times "vadd.f32" 16 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c index edc2f2f3bc6..9ab05e95420 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c @@ -1,6 +1,6 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2 -fno-ipa-icf" } */ #include "arm_mve.h" int8x16_t value1; @@ -41,4 +41,4 @@ foo1 () return vaddq_s16 (r7, vreinterpretq_s16 (value9)); } -/* { dg-final { scan-assembler-times "vadd.i16" 8 } } */ +/* { dg-final { scan-assembler-times "vadd.i16" 16 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c index 880de06a781..fbfff1fc1bb 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c @@ -1,6 +1,6 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2 -fno-ipa-icf" } */ #include "arm_mve.h" int16x8_t value1; @@ -41,4 +41,4 @@ foo1 () return vaddq_s32 (r7, vreinterpretq_s32 (value9)); } -/* { dg-final { scan-assembler-times "vadd.i32" 8 } } */ +/* { dg-final { scan-assembler-times "vadd.i32" 16 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c index b0e81542956..beb6b927deb 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c @@ -1,6 +1,6 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2 -fno-ipa-icf" } */ #include "arm_mve.h" int16x8_t value1; @@ -42,4 +42,4 @@ foo1 (mve_pred16_t __p) return vpselq_s64 (r7, vreinterpretq_s64 (value9), __p); } -/* { dg-final { scan-assembler-times "vpsel" 8 } } */ +/* { dg-final { scan-assembler-times "vpsel" 16 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c index a5ceebb10b9..727d89b63ee 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c @@ -1,6 +1,6 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2 -fno-ipa-icf" } */ #include "arm_mve.h" int16x8_t value1; @@ -41,4 +41,4 @@ foo1 () return vaddq_s8 (r7, vreinterpretq_s8 (value9)); } -/* { dg-final { scan-assembler-times "vadd.i8" 8 } } */ +/* { dg-final { scan-assembler-times "vadd.i8" 16 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c index cd31c23500a..600f6d72a96 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c @@ -1,6 +1,6 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2 -fno-ipa-icf" } */ #include "arm_mve.h" int8x16_t value1; @@ -41,4 +41,4 @@ foo1 () return vaddq_u16 (r7, vreinterpretq_u16 (value9)); } -/* { dg-final { scan-assembler-times "vadd.i16" 8 } } */ +/* { dg-final { scan-assembler-times "vadd.i16" 16 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c index faa66c9e1cc..d536ae825de 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c @@ -1,6 +1,6 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2 -fno-ipa-icf" } */ #include "arm_mve.h" int16x8_t value1; @@ -41,4 +41,4 @@ foo1 () return vaddq_u32 (r7, vreinterpretq_u32 (value9)); } -/* { dg-final { scan-assembler-times "vadd.i32" 8 } } */ +/* { dg-final { scan-assembler-times "vadd.i32" 16 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c index 853b28a2aac..abc43612b91 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c @@ -1,6 +1,6 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2 -fno-ipa-icf" } */ #include "arm_mve.h" int16x8_t value1; @@ -42,4 +42,4 @@ foo1 (mve_pred16_t __p) return vpselq_u64 (r7, vreinterpretq_u64 (value9), __p); } -/* { dg-final { scan-assembler-times "vpsel" 8 } } */ +/* { dg-final { scan-assembler-times "vpsel" 16 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c index bdf8cd588e1..c138e5b3668 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c @@ -1,6 +1,6 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2 -fno-ipa-icf" } */ #include "arm_mve.h" int16x8_t value1; @@ -41,4 +41,4 @@ foo1 () return vaddq_u8 (r7, vreinterpretq_u8 (value9)); } -/* { dg-final { scan-assembler-times "vadd.i8" 8 } } */ +/* { dg-final { scan-assembler-times "vadd.i8" 16 } } */