From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 11 Jul 2020 20:06:51 +0000 (+0100)
Subject: more setting bigendian
X-Git-Tag: div_pipeline~92
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=29cd58a6e1cbf4a18a047130c3151a0325e7c381;p=soc.git

more setting bigendian
---

diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index 2e60086f..592394c6 100644
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -12,7 +12,7 @@ import unittest
 from soc.decoder.isa.caller import special_sprs
 from soc.decoder.isa.all import ISA
 from soc.decoder.power_enums import Function, XER_bits
-
+from soc.config.endian import bigendian
 
 from soc.simple.issuer import TestIssuer
 from soc.experiment.compalu_multi import find_ok # hack
@@ -100,7 +100,7 @@ class TestRunner(FHDLTestCase):
             for test in self.test_data:
 
                 # get core going
-                yield core.bigendian_i.eq(1)
+                yield core.bigendian_i.eq(bigendian)
                 yield core.core_start_i.eq(1)
                 yield
                 yield core.core_start_i.eq(0)
@@ -121,7 +121,8 @@ class TestRunner(FHDLTestCase):
                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
                           test.msr,
                           initial_insns=gen, respect_pc=True,
-                          disassembly=insncode)
+                          disassembly=insncode,
+                          bigendian=bigendian)
 
                 pc = 0 # start address
 
diff --git a/src/soc/simple/test/test_microwatt.py b/src/soc/simple/test/test_microwatt.py
index 1abfa8ea..3ffa9e52 100644
--- a/src/soc/simple/test/test_microwatt.py
+++ b/src/soc/simple/test/test_microwatt.py
@@ -85,7 +85,7 @@ class TestRunner(FHDLTestCase):
             for test in self.test_data:
 
                 # get core going
-                yield core.bigendian_i.eq(1)
+                yield core.bigendian_i.eq(bigendian)
                 yield core.core_start_i.eq(1)
                 yield
                 yield core.core_start_i.eq(0)