From: Luke Kenneth Casson Leighton Date: Fri, 22 May 2020 15:15:16 +0000 (+0100) Subject: move CR over to CompCROpSubset X-Git-Tag: div_pipeline~943 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=29cf6251cd9ef025844f030d9120db90c32a2746;p=soc.git move CR over to CompCROpSubset --- diff --git a/src/soc/fu/cr/cr_input_record.py b/src/soc/fu/cr/cr_input_record.py index 7147ec2c..d5ffe87e 100644 --- a/src/soc/fu/cr/cr_input_record.py +++ b/src/soc/fu/cr/cr_input_record.py @@ -13,6 +13,7 @@ class CompCROpSubset(Record): def __init__(self, name=None): layout = (('insn_type', InternalOp), ('fn_unit', Function), + ('insn', 32), ('read_cr_whole', 1), ('write_cr_whole', 1), ) @@ -21,6 +22,7 @@ class CompCROpSubset(Record): # grrr. Record does not have kwargs self.insn_type.reset_less = True + self.insn.reset_less = True self.fn_unit.reset_less = True self.read_cr_whole.reset_less = True self.write_cr_whole.reset_less = True @@ -36,6 +38,7 @@ class CompCROpSubset(Record): def ports(self): return [self.insn_type, + self.insn, self.fn_unit, self.read_cr_whole, self.write_cr_whole, diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py index e59a81eb..2894144f 100644 --- a/src/soc/fu/cr/pipe_data.py +++ b/src/soc/fu/cr/pipe_data.py @@ -1,7 +1,7 @@ from nmigen import Signal, Const from ieee754.fpcommon.getop import FPPipeContext from soc.fu.pipe_data import IntegerData, CommonPipeSpec -from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace +from soc.fu.cr.cr_input_record import CompCROpSubset from soc.decoder.power_decoder2 import Data @@ -58,7 +58,6 @@ class CROutputData(IntegerData): self.full_cr.eq(i.full_cr), self.cr_o.eq(i.cr_o)] -# TODO: replace CompALUOpSubset with CompCROpSubset class CRPipeSpec(CommonPipeSpec): regspec = (CRInputData.regspec, CROutputData.regspec) - opsubsetkls = CompALUOpSubset + opsubsetkls = CompCROpSubset