From: Uros Bizjak <ubizjak@gmail.com>
Date: Wed, 11 Jul 2007 18:42:44 +0000 (+0200)
Subject: re PR target/32661 (__builtin_ia32_vec_ext suboptimal for pointer/ref args)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=29d27fb08aec801d22c941f9d41fbed91257ddfa;p=gcc.git

re PR target/32661 (__builtin_ia32_vec_ext suboptimal for pointer/ref args)

        PR target/32661
        * config/i386/sse.md (*sse2_storeq_rex64): Handle 64bit mem->reg moves.
        (*vec_extractv2di_1_sse2): Disable for TARGET_64BIT.
        (*vec_extractv2di_1_rex64): New insn pattern.

testsuite/ChangeLog:

        PR target/32661
        * gcc.target/i386/pr32661-1.c: New test.

From-SVN: r126557
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9b6a348be30..1e17ad3b6c4 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2007-07-11  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/32661
+	* config/i386/sse.md (*sse2_storeq_rex64): Handle 64bit mem->reg moves.
+	(*vec_extractv2di_1_sse2): Disable for TARGET_64BIT.
+	(*vec_extractv2di_1_rex64): New insn pattern.
+
 2007-07-11  David Daney  <ddaney@avtrex.com>
 
 	* config/mips/linux-unwind.h (mips_fallback_frame_state): Rewrite
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 027d43bfb6c..3164077862a 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -4587,12 +4587,17 @@
   "")
 
 (define_insn "*sse2_storeq_rex64"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=mx,r")
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=mx,r,r")
 	(vec_select:DI
-	  (match_operand:V2DI 1 "register_operand" "x,Yi")
+	  (match_operand:V2DI 1 "nonimmediate_operand" "x,Yi,o")
 	  (parallel [(const_int 0)])))]
-  "TARGET_64BIT && TARGET_SSE"
-  "#")
+  "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+  "@
+   #
+   #
+   mov{q}\t{%1, %0|%0, %1}"
+  [(set_attr "type" "*,*,imov")
+   (set_attr "mode" "*,*,DI")])
 
 (define_insn "*sse2_storeq"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=mx")
@@ -4617,12 +4622,28 @@
   operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));
 })
 
+(define_insn "*vec_extractv2di_1_rex64"
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x,r")
+	(vec_select:DI
+	  (match_operand:V2DI 1 "nonimmediate_operand" "x,0,o,o")
+	  (parallel [(const_int 1)])))]
+  "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+  "@
+   movhps\t{%1, %0|%0, %1}
+   psrldq\t{$8, %0|%0, 8}
+   movq\t{%H1, %0|%0, %H1}
+   mov{q}\t{%H1, %0|%0, %H1}"
+  [(set_attr "type" "ssemov,sseishft,ssemov,imov")
+   (set_attr "memory" "*,none,*,*")
+   (set_attr "mode" "V2SF,TI,TI,DI")])
+
 (define_insn "*vec_extractv2di_1_sse2"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x")
 	(vec_select:DI
 	  (match_operand:V2DI 1 "nonimmediate_operand" "x,0,o")
 	  (parallel [(const_int 1)])))]
-  "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+  "!TARGET_64BIT
+   && TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
   "@
    movhps\t{%1, %0|%0, %1}
    psrldq\t{$8, %0|%0, 8}
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 00456185681..02d37a000a4 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2007-07-11  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/32661
+	* gcc.target/i386/pr32661-1.c: New test.
+
 2007-07-11  Eric Botcazou  <ebotcazou@adacore.com>
 
 	* gnat.dg/invariant_index.ad[sb]: New test.
diff --git a/gcc/testsuite/gcc.target/i386/pr32661-1.c b/gcc/testsuite/gcc.target/i386/pr32661-1.c
new file mode 100644
index 00000000000..0354fc3421e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr32661-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { { i?86-*-* x86_64-*-* } && lp64 } } } */
+/* { dg-options "-O2" } */
+
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+
+long long foo_0(__m128i* val)
+{
+  return __builtin_ia32_vec_ext_v2di(*val, 0);
+}
+
+long long foo_1(__m128i* val)
+{
+  return __builtin_ia32_vec_ext_v2di(*val, 1);
+}
+
+/* { dg-final { scan-assembler-times "mov" 2 } } */