From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 17:39:00 +0000 (-0700)
Subject: Cleanup
X-Git-Tag: working-ls180~1039^2~97
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=29d446d7584b772a2dbac92a3088f93223ff7f86;p=yosys.git

Cleanup
---

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 08cb1f51b..31ab75f09 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -398,10 +398,8 @@ endmatch
 
 code argQ argD
 {
-	if (clock != SigBit()) {
-		if (port(ff, \CLK) != clock)
-			reject;
-	}
+	if (clock != SigBit() && port(ff, \CLK) != clock)
+		reject;
 
 	SigSpec Q = port(ff, \Q);
 	if (ffoffset + GetSize(argQ) > GetSize(Q))
@@ -580,10 +578,8 @@ endmatch
 
 code argQ
 	if (ff) {
-		if (clock != SigBit()) {
-			if (port(ff, \CLK) != clock)
-				reject;
-		}
+		if (clock != SigBit() && port(ff, \CLK) != clock)
+			reject;
 
 		SigSpec D = port(ff, \D);
 		if (ffoffset + GetSize(argD) > GetSize(D))