From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 24 Sep 2019 02:52:54 +0000 (-0700)
Subject: Revert "Vivado does not like zero width port connections"
X-Git-Tag: working-ls180~1039^2~35
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=29db96fa1ff89a8224f8ae3c51c754e16a34c31c;p=yosys.git

Revert "Vivado does not like zero width port connections"

This reverts commit 895e2befa76bd326cc47fd40de112ea067fcaf98.
---

diff --git a/techlibs/xilinx/xilinx_finalise.cc b/techlibs/xilinx/xilinx_finalise.cc
index 2c0bd3534..db73babe3 100644
--- a/techlibs/xilinx/xilinx_finalise.cc
+++ b/techlibs/xilinx/xilinx_finalise.cc
@@ -53,7 +53,7 @@ struct XilinxFinalisePass : public Pass
 		for (auto cell : module->selected_cells()) {
 			if (cell->type != ID(DSP48E1))
 				continue;
-			for (auto conn : cell->connections()) {
+			for (auto &conn : cell->connections_) {
 				if (!cell->output(conn.first))
 					continue;
 				bool purge = true;
@@ -74,7 +74,7 @@ struct XilinxFinalisePass : public Pass
 
 				if (purge) {
 					log_debug("Purging unused port connection %s %s (.%s(%s))\n", cell->type.c_str(), log_id(cell), log_id(conn.first), log_signal(conn.second));
-					cell->unsetPort(conn.first);
+					conn.second = SigSpec();
 				}
 			}
 		}