From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 11 Oct 2019 19:49:11 +0000 (+0200)
Subject: interconnect/wishbone: fix Converter case when buses are identical
X-Git-Tag: 24jan2021_ls180~914
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=29e51f5e97fabc4fd55b14927bdb0e7edb2cb960;p=litex.git

interconnect/wishbone: fix Converter case when buses are identical
---

diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py
index d32799b6..1fbdf975 100644
--- a/litex/soc/interconnect/wishbone.py
+++ b/litex/soc/interconnect/wishbone.py
@@ -486,7 +486,7 @@ class Converter(Module):
             upconverter = UpConverter(master, slave)
             self.submodules += upconverter
         else:
-            master.connect(slave)
+            self.comb += master.connect(slave)
 
 
 class Cache(Module):