From: Luke Kenneth Casson Leighton Date: Fri, 2 Sep 2022 14:43:17 +0000 (+0100) Subject: add svshape2 (stub pseudocode) fields, Form, and CSV file minor_22.csv X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=29ea1c07e1632b99c94371cc6da9b181283e7995;p=openpower-isa.git add svshape2 (stub pseudocode) fields, Form, and CSV file minor_22.csv https://bugs.libre-soc.org/show_bug.cgi?id=911 also added missing SVI-Form (svindex) SVd and rmm which are exactly the same. svshape2 is weird, it is a hybrid of svindex and svshapes --- diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn index e177b04d..22cb28ee 100644 --- a/openpower/isa/simplev.mdwn +++ b/openpower/isa/simplev.mdwn @@ -342,3 +342,21 @@ Special Registers Altered: None +# svshape2 + +SVM2-Form + +* svshape2 offs,yx,rmm,SVd,sk,mm + +Pseudo-code: + + # TODO. (placeholder: clear out all SVSHAPEs) + SVSHAPE0[0:31] <- [0] * 32 + SVSHAPE1[0:31] <- [0] * 32 + SVSHAPE2[0:31] <- [0] * 32 + SVSHAPE3[0:31] <- [0] * 32 + +Special Registers Altered: + + None + diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text index 7037463c..f783a3d1 100644 --- a/openpower/isatables/fields.text +++ b/openpower/isatables/fields.text @@ -306,6 +306,10 @@ |0 |6 |11 |16 |21 |25 |26 |31 | | PO | SVxd | SVyd | SVzd | SVrm |vf | XO | +# 1.6.35.1 SVM2-FORM + |0 |6 |10|11 |16 |21 |24|25 |26 |31 | + | PO | offs |yx| rmm | SVd |XO |mm|vf | XO | + # 1.6.36 SVRM-FORM |0 |6 |11 |13 |15 |17 |19 |21 |22 |26 |31 | | PO | SVme |mi0 | mi1 | mi2 | mo0 | mo1 |pst |/// | XO | @@ -651,7 +655,8 @@ Formats: SVRM mm (24) Field used to specify the meaning of the rmm field for SVI-Form - Formats: SVI + and SVM2-Form + Formats: SVI, SVM2 mo0 (17:18) Field used in REMAP to select the SVSHAPE for 1st output register Formats: SVRM @@ -669,6 +674,9 @@ Field used to specify the number of bytes to move in an immediate Move Assist instruction. Formats: X + offs (6:10) + Field used by the svshape2 instruction as an offset + Formats: SVM2 OC (6:20) Field used by the Embedded Hypervisor Privilege instruction. @@ -744,6 +752,9 @@ Immediate field used for DFP rounding mode con- trol. Formats: Z23 + rmm (11:15) + REMAP Mode field for SVI-Form and SVM2-Form + Formats: SVI, SVM2 RO (31) Round to Odd override Formats: X @@ -831,8 +842,8 @@ Formats: X SVd (16:20) Immediate field used to specify the size of the REMAP dimension - in the svindex instruction. - Formats: SVI + in the svindex and svshape2 instructions + Formats: SVI, SVM2 SVD (21:31) Immediate field used to specify an 11-bit signed two's complement integer which is sign-extended @@ -953,7 +964,7 @@ Formats: DS, VA, VC, VX, X vf (25) Field used in Simple-V to specify whether "Vertical" Mode is set - Formats: SVL, SVM + Formats: SVL, SVM, SVM2 vs (24) Field used in Simple-V to specify whether VL is to be set Formats: SVL @@ -974,6 +985,9 @@ Field used to specify a 6-bit unsigned immediate for bit manipulation instructions, such as grevi. Formats: XB + XO (21:23,26:31) + Extended opcode field. + Formats: SVM2 XO (21,23:31) Extended opcode field. Formats: VX diff --git a/openpower/isatables/minor_22.csv b/openpower/isatables/minor_22.csv index f6b1ffac..8f29693b 100644 --- a/openpower/isatables/minor_22.csv +++ b/openpower/isatables/minor_22.csv @@ -21,6 +21,8 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 1101-011001,VL,OP_SVSHAPE,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,svshape,SVM,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1110-011001,VL,OP_SVSHAPE,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,svshape,SVM,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1111-011001,VL,OP_SVSHAPE,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,svshape,SVM,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# svshape2: {-100,mm,011001} +-100-011001,VL,OP_SVSHAPE,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,svshape2,SVM,,1,unofficial until submitted and approved/renumbered by the opf isa wg # A/V bitmanip 0111001110-,ALU,OP_MINMAX,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,maxs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 0011001110-,ALU,OP_MINMAX,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,maxu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index c4f85d14..9cbc8232 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -161,6 +161,7 @@ class Form(Enum): SVD = 30 # Simple-V for LD/ST bit-reverse, variant of D-Form SVDS = 31 # Simple-V for LD/ST bit-reverse, variant of DS-Form SVM = 32 # Simple-V SHAPE mode + SVM2 = 33 # Simple-V SHAPE2 mode - fits into SVM SVRM = 34 # Simple-V REMAP mode TLI = 35 # ternlogi XB = 36