From: Daniel R. Carvalho Date: Fri, 8 Mar 2019 16:41:25 +0000 (+0100) Subject: mem-cache: Revert "mem-cache: Remove Packet dependency in Tags" X-Git-Tag: v19.0.0.0~1067 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=29f68cc7ba4c9d4c1e07806ae226d148a8a25e0e;p=gem5.git mem-cache: Revert "mem-cache: Remove Packet dependency in Tags" Reverting patch due to polymorphism limitations. This reverts commit 86a54d91936b524c0ef0f282959f0fc29bafe7eb. Change-Id: Ie032dcc5176448c62118c89732b3cc6b8efd5a13 Signed-off-by: Daniel R. Carvalho Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17049 Reviewed-by: Giacomo Travaglini Reviewed-by: Jason Lowe-Power Reviewed-by: Nikos Nikoleris Maintainer: Nikos Nikoleris --- diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index a42f2ebda..9f708b30d 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -1359,8 +1359,7 @@ BaseCache::allocateBlock(const PacketPtr pkt, PacketList &writebacks) } // Insert new block at victimized entry - tags->insertBlock(addr, is_secure, pkt->req->masterId(), - pkt->req->taskId(), victim); + tags->insertBlock(pkt, victim); return victim; } diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc index 7237f1821..4855ebd51 100644 --- a/src/mem/cache/tags/base.cc +++ b/src/mem/cache/tags/base.cc @@ -98,20 +98,21 @@ BaseTags::findBlock(Addr addr, bool is_secure) const } void -BaseTags::insertBlock(const Addr addr, const bool is_secure, - const int src_master_ID, const uint32_t task_ID, - CacheBlk *blk) +BaseTags::insertBlock(const PacketPtr pkt, CacheBlk *blk) { assert(!blk->isValid()); // Previous block, if existed, has been removed, and now we have // to insert the new one + // Deal with what we are bringing in - assert(src_master_ID < system->maxMasters()); - occupancies[src_master_ID]++; + MasterID master_id = pkt->req->masterId(); + assert(master_id < system->maxMasters()); + occupancies[master_id]++; // Insert block with tag, src master id and task id - blk->insert(extractTag(addr), is_secure, src_master_ID, task_ID); + blk->insert(extractTag(pkt->getAddr()), pkt->isSecure(), master_id, + pkt->req->taskId()); // Check if cache warm up is done if (!warmedUp && tagsInUse.value() >= warmupBound) { diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh index 840193b7a..296837e50 100644 --- a/src/mem/cache/tags/base.hh +++ b/src/mem/cache/tags/base.hh @@ -58,6 +58,7 @@ #include "base/statistics.hh" #include "base/types.hh" #include "mem/cache/cache_blk.hh" +#include "mem/packet.hh" #include "params/BaseTags.hh" #include "sim/clocked_object.hh" @@ -305,15 +306,10 @@ class BaseTags : public ClockedObject /** * Insert the new block into the cache and update stats. * - * @param addr Address of the block. - * @param is_secure Whether the block is in secure space or not. - * @param src_master_ID The source requestor ID. - * @param task_ID The new task ID. + * @param pkt Packet holding the address to update * @param blk The block to update. */ - virtual void insertBlock(const Addr addr, const bool is_secure, - const int src_master_ID, const uint32_t task_ID, - CacheBlk *blk); + virtual void insertBlock(const PacketPtr pkt, CacheBlk *blk); /** * Regenerate the block address. diff --git a/src/mem/cache/tags/base_set_assoc.hh b/src/mem/cache/tags/base_set_assoc.hh index b1fa88464..c39a81335 100644 --- a/src/mem/cache/tags/base_set_assoc.hh +++ b/src/mem/cache/tags/base_set_assoc.hh @@ -60,6 +60,7 @@ #include "mem/cache/replacement_policies/replaceable_entry.hh" #include "mem/cache/tags/base.hh" #include "mem/cache/tags/indexing_policies/base.hh" +#include "mem/packet.hh" #include "params/BaseSetAssoc.hh" /** @@ -182,18 +183,13 @@ class BaseSetAssoc : public BaseTags /** * Insert the new block into the cache and update replacement data. * - * @param addr Address of the block. - * @param is_secure Whether the block is in secure space or not. - * @param src_master_ID The source requestor ID. - * @param task_ID The new task ID. + * @param pkt Packet holding the address to update * @param blk The block to update. */ - void insertBlock(const Addr addr, const bool is_secure, - const int src_master_ID, const uint32_t task_ID, - CacheBlk *blk) override + void insertBlock(const PacketPtr pkt, CacheBlk *blk) override { // Insert block - BaseTags::insertBlock(addr, is_secure, src_master_ID, task_ID, blk); + BaseTags::insertBlock(pkt, blk); // Increment tag counter tagsInUse++; diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc index b1f9bbc92..4cdac0ac0 100644 --- a/src/mem/cache/tags/fa_lru.cc +++ b/src/mem/cache/tags/fa_lru.cc @@ -209,9 +209,7 @@ FALRU::findVictim(Addr addr, const bool is_secure, } void -FALRU::insertBlock(const Addr addr, const bool is_secure, - const int src_master_ID, const uint32_t task_ID, - CacheBlk *blk) +FALRU::insertBlock(const PacketPtr pkt, CacheBlk *blk) { FALRUBlk* falruBlk = static_cast(blk); @@ -219,7 +217,7 @@ FALRU::insertBlock(const Addr addr, const bool is_secure, assert(falruBlk->inCachesMask == 0); // Do common block insertion functionality - BaseTags::insertBlock(addr, is_secure, src_master_ID, task_ID, blk); + BaseTags::insertBlock(pkt, blk); // Increment tag counter tagsInUse++; diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh index 0cae1dea6..346ff60c7 100644 --- a/src/mem/cache/tags/fa_lru.hh +++ b/src/mem/cache/tags/fa_lru.hh @@ -62,6 +62,7 @@ #include "base/types.hh" #include "mem/cache/cache_blk.hh" #include "mem/cache/tags/base.hh" +#include "mem/packet.hh" #include "params/FALRU.hh" // Uncomment to enable sanity checks for the FALRU cache and the @@ -227,15 +228,10 @@ class FALRU : public BaseTags /** * Insert the new block into the cache and update replacement data. * - * @param addr Address of the block. - * @param is_secure Whether the block is in secure space or not. - * @param src_master_ID The source requestor ID. - * @param task_ID The new task ID. + * @param pkt Packet holding the address to update * @param blk The block to update. */ - void insertBlock(const Addr addr, const bool is_secure, - const int src_master_ID, const uint32_t task_ID, - CacheBlk *blk) override; + void insertBlock(const PacketPtr pkt, CacheBlk *blk) override; /** * Generate the tag from the addres. For fully associative this is just the diff --git a/src/mem/cache/tags/sector_tags.cc b/src/mem/cache/tags/sector_tags.cc index ad374e5ee..0cd73719e 100644 --- a/src/mem/cache/tags/sector_tags.cc +++ b/src/mem/cache/tags/sector_tags.cc @@ -167,9 +167,7 @@ SectorTags::accessBlock(Addr addr, bool is_secure, Cycles &lat) } void -SectorTags::insertBlock(const Addr addr, const bool is_secure, - const int src_master_ID, const uint32_t task_ID, - CacheBlk *blk) +SectorTags::insertBlock(const PacketPtr pkt, CacheBlk *blk) { // Get block's sector SectorSubBlk* sub_blk = static_cast(blk); @@ -189,7 +187,7 @@ SectorTags::insertBlock(const Addr addr, const bool is_secure, } // Do common block insertion functionality - BaseTags::insertBlock(addr, is_secure, src_master_ID, task_ID, blk); + BaseTags::insertBlock(pkt, blk); } CacheBlk* diff --git a/src/mem/cache/tags/sector_tags.hh b/src/mem/cache/tags/sector_tags.hh index e3c0fa447..8e389a6a6 100644 --- a/src/mem/cache/tags/sector_tags.hh +++ b/src/mem/cache/tags/sector_tags.hh @@ -41,9 +41,9 @@ #include "mem/cache/tags/base.hh" #include "mem/cache/tags/sector_blk.hh" +#include "mem/packet.hh" #include "params/SectorTags.hh" -class BaseCache; class BaseReplacementPolicy; class ReplaceableEntry; @@ -129,15 +129,10 @@ class SectorTags : public BaseTags /** * Insert the new block into the cache and update replacement data. * - * @param addr Address of the block. - * @param is_secure Whether the block is in secure space or not. - * @param src_master_ID The source requestor ID. - * @param task_ID The new task ID. + * @param pkt Packet holding the address to update * @param blk The block to update. */ - void insertBlock(const Addr addr, const bool is_secure, - const int src_master_ID, const uint32_t task_ID, - CacheBlk *blk) override; + void insertBlock(const PacketPtr pkt, CacheBlk *blk) override; /** * Finds the given address in the cache, do not update replacement data.