From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Sun, 24 Nov 2013 22:43:14 +0000 (+0100)
Subject: bus/wishbone/sram: expose memory component
X-Git-Tag: 24jan2021_ls180~2099^2~435
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=29f7b94e37cc4fb0affe62258efe10d3ceb1db29;p=litex.git

bus/wishbone/sram: expose memory component
---

diff --git a/migen/bus/wishbone.py b/migen/bus/wishbone.py
index fec23a18..6dd2a066 100644
--- a/migen/bus/wishbone.py
+++ b/migen/bus/wishbone.py
@@ -288,20 +288,20 @@ class SRAM(Module):
 		bus_data_width = flen(self.bus.dat_r)
 		if isinstance(mem_or_size, Memory):
 			assert(mem_or_size.width <= bus_data_width)
-			mem = mem_or_size
+			self.mem = mem_or_size
 		else:
-			mem = Memory(bus_data_width, mem_or_size//(bus_data_width//8), init=init)
+			self.mem = Memory(bus_data_width, mem_or_size//(bus_data_width//8), init=init)
 		if read_only is None:
-			if hasattr(mem, "bus_read_only"):
-				read_only = mem.bus_read_only
+			if hasattr(self.mem, "bus_read_only"):
+				read_only = self.mem.bus_read_only
 			else:
 				read_only = False
 	
 		###
 	
 		# memory
-		port = mem.get_port(write_capable=not read_only, we_granularity=8)
-		self.specials += mem, port
+		port = self.mem.get_port(write_capable=not read_only, we_granularity=8)
+		self.specials += self.mem, port
 		# generate write enable signal
 		if not read_only:
 			self.comb += [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])