From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 18 Dec 2021 01:57:04 +0000 (+0000)
Subject: move connection of bus.stall in icache.py,
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2a0395f042abfa6b774418e2ec3c27a4e8da2f04;p=soc.git

move connection of bus.stall in icache.py,
only create a fake bus.stall if ibus does not have a stall signal
---

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 2e5b33f3..5417c8b3 100644
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -834,10 +834,6 @@ class ICache(FetchUnitInterface, Elaboratable):
         plru_victim      = Signal(WAY_BITS)
         replace_way      = Signal(WAY_BITS)
 
-        # fake-up the wishbone stall signal to comply with pipeline mode
-        # same thing is done in dcache.py
-        comb += self.bus.stall.eq(self.bus.cyc & ~self.bus.ack)
-
         # call sub-functions putting everything together,
         # using shared signals established above
         self.rams(m, r, cache_out_row, use_previous, replace_way, req_row)
@@ -887,6 +883,10 @@ class ICache(FetchUnitInterface, Elaboratable):
         comb += self.bus.ack.eq(ibus.ack)
         if hasattr(ibus, "stall"):
             comb += self.bus.stall.eq(ibus.stall)
+        else:
+            # fake-up the wishbone stall signal to comply with pipeline mode
+            # same thing is done in dcache.py
+            comb += self.bus.stall.eq(self.bus.cyc & ~self.bus.ack)
 
         return m