From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 19 Oct 2018 11:03:38 +0000 (+0200)
Subject: Merge pull request #670 from rubund/feature/basic_svinterface_test
X-Git-Tag: yosys-0.9~438
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2a104b29fd7e504bdedb27c286cf9125d46dfd55;p=yosys.git

Merge pull request #670 from rubund/feature/basic_svinterface_test

Basic test for checking correct synthesis of SystemVerilog interfaces
---

2a104b29fd7e504bdedb27c286cf9125d46dfd55