From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Wed, 1 Apr 2015 07:48:56 +0000 (+0800)
Subject: soc: simplify/fix csr busword
X-Git-Tag: 24jan2021_ls180~2416
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2a1112b912b3ac56d6a62372a778706ac0463e79;p=litex.git

soc: simplify/fix csr busword
---

diff --git a/misoclib/soc/__init__.py b/misoclib/soc/__init__.py
index 132a650f..bb454200 100644
--- a/misoclib/soc/__init__.py
+++ b/misoclib/soc/__init__.py
@@ -177,9 +177,9 @@ class SoC(Module):
 				data_width=self.csr_data_width, address_width=self.csr_address_width)
 			self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
 			for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
-				self.add_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
+				self.add_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, self.csr_data_width, csrs)
 			for name, memory, mapaddr, mmap in self.csrbankarray.srams:
-				self.add_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
+				self.add_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, self.csr_data_width, memory)
 
 		# Interrupts
 		if hasattr(self.cpu_or_bridge, "interrupt"):