From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 8 Mar 2020 18:27:15 +0000 (+0000)
Subject: take XER out of decode, it is from the CR regfile
X-Git-Tag: div_pipeline~1753
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2a1a604561f23927231220d7478a90b67e9f052f;p=soc.git

take XER out of decode, it is from the CR regfile
---

diff --git a/src/decoder/power_decoder2.py b/src/decoder/power_decoder2.py
index 5d706d93..c7140a6e 100644
--- a/src/decoder/power_decoder2.py
+++ b/src/decoder/power_decoder2.py
@@ -280,7 +280,7 @@ class Decode2ToExecute1Type:
         self.read_data2 = Signal(64, reset_less=True)
         self.read_data3 = Signal(64, reset_less=True)
         self.cr = Signal(32, reset_less=True)
-        self.xerc = XerBits()
+        #self.xerc = XerBits() # NO: this is from the XER SPR
         self.lk = Signal(reset_less=True)
         self.rc = Signal(reset_less=True)
         self.oe = Signal(reset_less=True)
@@ -309,7 +309,7 @@ class Decode2ToExecute1Type:
                 self.is_32bit, self.is_signed,
                 self.insn,
                 self.data_len, self.byte_reverse , self.sign_extend ,
-                self.update] + self.xerc.ports()
+                self.update] # + self.xerc.ports()
 
 
 class PowerDecode2(Elaboratable):