From: programmerjake@6415f89267377da4199b62e82acfa94913226af1 <programmerjake@web>
Date: Sun, 1 Sep 2019 16:23:27 +0000 (+0100)
Subject: fix formatting
X-Git-Tag: convert-csv-opcode-to-binary~4173
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2a232016881435d593b5cb4480ac72954c3e102e;p=libreriscv.git

fix formatting
---

diff --git a/simple_v_extension/vblock_format/discussion.mdwn b/simple_v_extension/vblock_format/discussion.mdwn
index 98a1820c9..c6949ee59 100644
--- a/simple_v_extension/vblock_format/discussion.mdwn
+++ b/simple_v_extension/vblock_format/discussion.mdwn
@@ -87,10 +87,10 @@ Example (contrived):
 
 Writing those out separately, for clarity:
 
-  ADD vector-x3, vector-x5, scalar-x12 # from vs1=1, vs2=0, vd=vs1|vs2
-  ADD vector-x7, vector-x5, vector-x3  # x7: v-x5 | v-x3
-  ADD scalar-x9, scalar-x4, scalar-x4  # x9, x4 not prefixed, therefore scalar
-  ADD vector-x7, vector-x5, scalar-x4  # x4 marked as scalar, x7, x5 vector
+  ADD vector-x3, vector-x5, scalar-x12 # from vs1=1, vs2=0, vd=vs1|vs2  
+  ADD vector-x7, vector-x5, vector-x3  # x7: v-x5 | v-x3  
+  ADD scalar-x9, scalar-x4, scalar-x4  # x9, x4 not prefixed, therefore scalar  
+  ADD vector-x7, vector-x5, scalar-x4  # x4 marked as scalar, x7, x5 vector  
 
 Twin-SVP mode allows certain registers to be explicitly marked as "scalar",
 where some of the rules might otherwise start to cascade through and cause