From: whitequark <cz@m-labs.hk>
Date: Thu, 12 Sep 2019 13:54:48 +0000 (+0000)
Subject: lib.cdc: make domain properties private.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2a4731849f53471b94def1e1ce958362c0f25c54;p=nmigen.git

lib.cdc: make domain properties private.

It is not correct to access domain properties from user code, because
it will not match the reality if DomainRenamer has been applied to
the module.
---

diff --git a/nmigen/compat/genlib/cdc.py b/nmigen/compat/genlib/cdc.py
index bbd97a1..b65fb4b 100644
--- a/nmigen/compat/genlib/cdc.py
+++ b/nmigen/compat/genlib/cdc.py
@@ -18,6 +18,7 @@ class MultiReg(NativeMultiReg):
                           .format(odomain, odomain),
                           DeprecationWarning, stacklevel=2)
         super().__init__(i, o, o_domain=odomain, n=n, reset=reset)
+        self.odomain = odomain
 
 
 @deprecated("instead of `migen.genlib.cdc.GrayCounter`, use `nmigen.lib.coding.GrayEncoder`")
diff --git a/nmigen/lib/cdc.py b/nmigen/lib/cdc.py
index 6d22714..3ed1077 100644
--- a/nmigen/lib/cdc.py
+++ b/nmigen/lib/cdc.py
@@ -52,8 +52,8 @@ class MultiReg(Elaboratable):
     def __init__(self, i, o, *, o_domain="sync", n=2, reset=0, reset_less=True):
         self.i = i
         self.o = o
-        self.o_domain = o_domain
 
+        self._o_domain = o_domain
         self._regs = [Signal(self.i.shape(), name="cdc{}".format(i), reset=reset,
                              reset_less=reset_less)
                       for i in range(n)]
@@ -64,7 +64,7 @@ class MultiReg(Elaboratable):
 
         m = Module()
         for i, o in zip((self.i, *self._regs), self._regs):
-            m.d[self.o_domain] += o.eq(i)
+            m.d[self._o_domain] += o.eq(i)
         m.d.comb += self.o.eq(self._regs[-1])
         return m
 
@@ -72,8 +72,8 @@ class MultiReg(Elaboratable):
 class ResetSynchronizer(Elaboratable):
     def __init__(self, arst, *, domain="sync", n=2):
         self.arst = arst
-        self.domain = domain
 
+        self._domain = domain
         self._regs = [Signal(1, name="arst{}".format(i), reset=1)
                       for i in range(n)]
 
@@ -86,8 +86,8 @@ class ResetSynchronizer(Elaboratable):
         for i, o in zip((0, *self._regs), self._regs):
             m.d.reset_sync += o.eq(i)
         m.d.comb += [
-            ClockSignal("reset_sync").eq(ClockSignal(self.domain)),
+            ClockSignal("reset_sync").eq(ClockSignal(self._domain)),
             ResetSignal("reset_sync").eq(self.arst),
-            ResetSignal(self.domain).eq(self._regs[-1])
+            ResetSignal(self._domain).eq(self._regs[-1])
         ]
         return m