From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 5 Jun 2021 17:08:44 +0000 (+0000)
Subject: sigh trying to find the right clock line
X-Git-Tag: LS180_RC3~27^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2a555f6d2670f3d01de4e48d8b8cc3cb61aef3b4;p=soclayout.git

sigh trying to find the right clock line
---

diff --git a/experiments9/doDesign.py b/experiments9/doDesign.py
index 0eba1cf..062c88d 100644
--- a/experiments9/doDesign.py
+++ b/experiments9/doDesign.py
@@ -58,8 +58,10 @@ def scriptMain (**kw):
         ls180Conf.chipConf.ioPadGauge = 'niolib'
         ls180Conf.coreSize = (l(coreSize     ), l(coreSize     ))
         ls180Conf.chipSize = (l(coreSize+3360), l(coreSize+3360))
-        ls180Conf.useHTree('por_clk') # output from the PLL, needs to be H-Tree
+        #ls180Conf.useHTree('core.por_clk') # output from the PLL, needs to be H-Tree
+        #ls180Conf.useHTree('test_issuer.pllclk_clk') # output from the PLL, needs to be H-Tree
         ls180Conf.useHTree('jtag_tck_from_pad')
+        ls180Conf.useHTree('sys_clk_from_pad')
 
         ls180ToChip = CoreToChip( ls180Conf )
         ls180ToChip.buildChip()