From: lkcl <lkcl@web>
Date: Tue, 4 Oct 2022 02:33:21 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~200
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2a61c8a667f1dee172d07dc8931079aaefabf12d;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/discussion.mdwn b/openpower/sv/svp64/discussion.mdwn
index 700454c19..a5ebcfe86 100644
--- a/openpower/sv/svp64/discussion.mdwn
+++ b/openpower/sv/svp64/discussion.mdwn
@@ -310,12 +310,18 @@ Element-Striding is specifically enabled on RA and RB being
 scalar.  If VL=1 behaviour is also activated then this is potentially
 interfered with, except that, again, RT may be set as a vector destination.
 
-
 ```
     if svctx.ldstmode == elementstride:
         EA = ireg[RA] + ireg[RB]*j   # register-strided
 ```
 
+Vector destination is again "VLSPLAT" mode, but if a Scalar
+destination was set with VL>1, then just as with LD-immediate
+it is the entire predicate mask which must be zero to stop
+the scalar element from being loaded, and the same effect may
+be achieved with VL=1 by ORing all predicate mask bits down to
+a single bit as a new predicate.
+
 ## answers to 4, loops/uses
 
 ### REMAP
@@ -341,7 +347,7 @@ with nonzeroing the application of a predicate mask to an all-scalar
 operation effectively tests **ALL** relevant bits 0..VL-1 as nonzero in the
 decision-making, whereas VL=1 will only test the first.
 
-a need for merging all bits into a single alternative predicate mask
+a need for merging (ORing) all bits into a single alternative predicate mask
 (single-bit) is the sort of thing we can probably live with.
 
 ### fast traditional packed SIMD