From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 18 May 2020 03:59:19 +0000 (+0100)
Subject: fix countzero import on test
X-Git-Tag: div_pipeline~1089
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2a6e4d09ed3e04c30c343d18358fd84967b68f3f;p=soc.git

fix countzero import on test
---

diff --git a/src/soc/fu/countzero/test/test_countzero.py b/src/soc/fu/countzero/test/test_countzero.py
index 60185196..b795920c 100644
--- a/src/soc/fu/countzero/test/test_countzero.py
+++ b/src/soc/fu/countzero/test/test_countzero.py
@@ -4,7 +4,7 @@ from nmigen.cli import rtlil
 from nmigen.back.pysim import Simulator, Delay
 from nmigen.test.utils import FHDLTestCase
 import unittest
-from soc.countzero.countzero import ZeroCounter
+from soc.fu.countzero.countzero import ZeroCounter
 
 
 class ZeroCounterTestCase(FHDLTestCase):