From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 5 Apr 2019 22:43:37 +0000 (+0100)
Subject: tidy up i_valid_logic
X-Git-Tag: ls180-24jan2020~1331
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2a71324d4934164ad8a697a55d765dc6cfec763e;p=ieee754fpu.git

tidy up i_valid_logic
---

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index 2cb7d1ab..02b82352 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -195,15 +195,20 @@ class PrevControl:
 
     def i_valid_logic(self):
         vlen = len(self.i_valid)
-        if vlen > 1: # multi-bit case: valid only when i_valid is all 1s
+        if vlen > 1:
+            # multi-bit case: valid only when i_valid is all 1s
             all1s = Const(-1, (len(self.i_valid), False))
-            if self.stage_ctl:
-                return self.i_valid == all1s & self.s_o_ready
-            return self.i_valid == all1s
-        # single-bit i_valid case
+            i_valid = (self.i_valid == all1s)
+        else:
+            # single-bit i_valid case
+            i_valid = self.i_valid
+
+        # when stage indicates not ready, incoming data
+        # must "appear" to be not ready too
         if self.stage_ctl:
-            return self.i_valid & self.s_o_ready
-        return self.i_valid
+            i_valid = i_valid & self.s_o_ready
+
+        return i_valid
 
 
 class NextControl: