From: lkcl <lkcl@web>
Date: Fri, 8 Jan 2021 20:51:36 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~532
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2a71605d69c7d3649b2d0247186eed8b6ca59811;p=libreriscv.git

---

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index f80b17eda..86acf073d 100644
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -46,7 +46,14 @@ a 4 operand variant which becomes more along the lines of an FPGA:
         idx = RT[i] << 2 | RA[i] << 1 | RB[i]
         RT[i] = (RC & (1<<idx)) != 0
 
-mode may be used to do inversion of ordering, similar to carryless mul
+mode (3 bit) may be used to do inversion of ordering, similar to carryless mul.
+
+also, another possible variant involving swizzle and vec4:
+
+    for i in range(8):
+        idx = RA.x[i] << 2 | RA.y[i] << 1 | RA.z[i]
+        RT[i] = (RA.w[i] & (1<<idx)) != 0
+
 
 another mode selection would be CRs not Ints.