From: lkcl <lkcl@web>
Date: Tue, 15 Dec 2020 14:06:08 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1314
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2a79053333875276fbe4a0d85dd2902ec47e7097;p=libreriscv.git

---

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index e973e50ef..8c6e8603e 100644
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -275,6 +275,9 @@ standard vector instruction with Rc=1.
 
 ## Alternative CR Vectorization Scheme
 
+CR[i] is the notation used by the OpenPower spec to refer to CR field #i,
+so FP instructions with Rc=1 write to CR[1] aka SVCR1_000.
+
 There are 3 new SPRs for holding CRs: CR_EXT1, CR_EXT2, and CR_EXT3.
 
 Arrange the 64 SV CRs similarly to the way the 128 integer registers are arranged: