From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 6 Jul 2019 09:39:20 +0000 (+0100)
Subject: fix overwrite issue in FPBase create
X-Git-Tag: ls180-24jan2020~909
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2a7919a0f52d47d4b4bf94b34932cef7f7d0ddb0;p=ieee754fpu.git

fix overwrite issue in FPBase create
---

diff --git a/src/ieee754/fcvt/pipeline.py b/src/ieee754/fcvt/pipeline.py
index b5323f7a..734f92c8 100644
--- a/src/ieee754/fcvt/pipeline.py
+++ b/src/ieee754/fcvt/pipeline.py
@@ -73,9 +73,6 @@ class FPCVTSpecialCasesMod(Elaboratable):
         z1 = self.o.z
         print ("z1", z1.width, z1.rmw, z1.e_width, z1.e_start, z1.e_end)
 
-        # set sign
-        m.d.comb += self.o.z.s.eq(a1.s)
-
         # intermediaries
         exp_sub_n126 = Signal((a1.e_width, True), reset_less=True)
         exp_gt127 = Signal(reset_less=True)
@@ -92,11 +89,13 @@ class FPCVTSpecialCasesMod(Elaboratable):
 
         # if a range outside z's min range (-126)
         with m.Elif(exp_sub_n126 < 0):
+            m.d.comb += self.o.z.s.eq(a1.s)
             m.d.comb += self.o.z.e.eq(a1.e)
             m.d.comb += self.o.z.m.eq(a1.m[-self.o.z.rmw-1:])
             m.d.comb += self.o.of.guard.eq(a1.m[-self.o.z.rmw-2])
             m.d.comb += self.o.of.round_bit.eq(a1.m[-self.o.z.rmw-3])
             m.d.comb += self.o.of.sticky.eq(a1.m[:-self.o.z.rmw-3] != 0)
+            m.d.comb += self.o.of.m0.eq(self.o.z.m[0])
 
         # if a is inf return inf 
         with m.Elif(a1.is_inf):
@@ -110,12 +109,12 @@ class FPCVTSpecialCasesMod(Elaboratable):
 
         # if a mantissa greater than 127, return inf
         with m.Elif(exp_gt127):
+            print ("inf", self.o.z.inf(a1.s))
             m.d.comb += self.o.z.inf(a1.s)
             m.d.comb += self.o.out_do_z.eq(1)
 
         # ok after all that, anything else should fit fine (whew)
         with m.Else():
-            m.d.comb += self.o.z.e.eq(a1.e)
             print ("alen", a1.e_start, z1.fp.N126, N126)
             print ("m1", self.o.z.rmw, a1.m[-self.o.z.rmw-1:])
             m.d.comb += self.o.z.create(a1.s, a1.e, a1.m[-self.o.z.rmw-1:])
diff --git a/src/ieee754/fpcommon/fpbase.py b/src/ieee754/fpcommon/fpbase.py
index ca889918..2ef543d4 100644
--- a/src/ieee754/fpcommon/fpbase.py
+++ b/src/ieee754/fpcommon/fpbase.py
@@ -125,12 +125,15 @@ class FPNumBaseRecord:
     def create(self, s, e, m):
         """ creates a value from sign / exponent / mantissa
 
-            bias is added here, to the exponent
+            bias is added here, to the exponent.
+
+            NOTE: order is important, because e_start/e_end can be
+            a bit too long (overwriting s).
         """
         return [
-          self.v[-1].eq(s),          # sign
+          self.v[0:self.e_start].eq(m),        # mantissa
           self.v[self.e_start:self.e_end].eq(e + self.fp.P127), # (add on bias)
-          self.v[0:self.e_start].eq(m)         # mantissa
+          self.v[-1].eq(s),          # sign
         ]
 
     def _nan(self, s):
diff --git a/src/ieee754/fpcommon/test/fpmux.py b/src/ieee754/fpcommon/test/fpmux.py
index 63871dad..446ebd0f 100644
--- a/src/ieee754/fpcommon/test/fpmux.py
+++ b/src/ieee754/fpcommon/test/fpmux.py
@@ -129,6 +129,7 @@ class InputTestRandom(InputTest):
                     #op1 = 0x40900000
                     #op1 = 0x94607b66
                     #op1 = 0x889cd8c
+                    #op1 = 0xe98646d7
                     vals.append((op1,))
                 else:
                     op1 = randint(0, (1<<width)-1)