From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Fri, 18 Sep 2020 14:08:52 +0000 (+0100)
Subject: arch-arm: Reimplement TLB::flushAll
X-Git-Tag: develop-gem5-snapshot~572
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2a91ea75861eb7749687deb2dea538ad39942c3d;p=gem5.git

arch-arm: Reimplement TLB::flushAll

flushAll is a non architectural flush command; this is not based on
flushAllSecurity anymore. flushAll should always flush stage1 and stage2,
whereas flushAllSecurity is checking for the current state
(vmid, and if we are in Hyp)

Change-Id: I6b81ebfba387e646f256ecbecb7b5ee720745358
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35239
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 0f9d7cde0..6f8b46f9e 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, 2016-2019 ARM Limited
+ * Copyright (c) 2010-2013, 2016-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -245,6 +245,29 @@ TLB::printTlb() const
     }
 }
 
+void
+TLB::flushAll()
+{
+    DPRINTF(TLB, "Flushing all TLB entries\n");
+    int x = 0;
+    TlbEntry *te;
+    while (x < size) {
+        te = &table[x];
+
+        DPRINTF(TLB, " -  %s\n", te->print());
+        te->valid = false;
+        stats.flushedEntries++;
+        ++x;
+    }
+
+    stats.flushTlb++;
+
+    // If there's a second stage TLB (and we're not it) then flush it as well
+    if (!isStage2) {
+        stage2Tlb->flushAll();
+    }
+}
+
 void
 TLB::flushAllSecurity(bool secure_lookup, ExceptionLevel target_el,
                       bool ignore_el, bool in_host)
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index f839848cb..6363b7c00 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, 2016, 2019 ARM Limited
+ * Copyright (c) 2010-2013, 2016, 2019-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -246,6 +246,11 @@ class TLB : public BaseTLB
     bool checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req,
                   Mode mode);
 
+    /** Reset the entire TLB. Used for CPU switching to prevent stale
+     * translations after multiple switches
+     */
+    void flushAll() override;
+
 
     /** Reset the entire TLB
      * @param secure_lookup if the operation affects the secure world
@@ -259,15 +264,6 @@ class TLB : public BaseTLB
     void flushAllNs(ExceptionLevel target_el, bool ignore_el = false);
 
 
-    /** Reset the entire TLB. Used for CPU switching to prevent stale
-     * translations after multiple switches
-     */
-    void flushAll() override
-    {
-        flushAllSecurity(false, EL0, true, false);
-        flushAllSecurity(true, EL0, true, false);
-    }
-
     /** Remove any entries that match both a va and asn
      * @param mva virtual address to flush
      * @param asn contextid/asn to flush on match