From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 5 Jun 2020 11:13:10 +0000 (+0100)
Subject: whoops connecting up CR in wrong order.  fixing with list sort
X-Git-Tag: div_pipeline~564
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2a95e1447c68f38dd40b4e6661e8c4f1331fb2cb;p=soc.git

whoops connecting up CR in wrong order.  fixing with list sort
---

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index a53ef5ab..ca44c11e 100644
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -82,7 +82,8 @@ class CRRegs(VirtualRegPort):
     def __init__(self):
         super().__init__(32, 8)
         self.w_ports = [self.full_wr, # 32-bit wide (masked, 8-en lines)
-                        self.write_port("dest")] # 4-bit wide, unary-indexed
+                        self.write_port("dest1"), # 4-bit wide, unary-indexed
+                        self.write_port("dest2")] # 4-bit wide, unary-indexed
         self.r_ports = [self.full_rd, # 32-bit wide (masked, 8-en lines)
                         self.read_port("src1"),
                         self.read_port("src2"),
diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index d543203a..0465e9d5 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -37,6 +37,17 @@ import operator
 def ortreereduce(tree, attr="data_o"):
     return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
 
+# helper function to place full regs declarations first
+def sort_fuspecs(fuspecs):
+    res = []
+    for (regname, fspec) in fuspecs.items():
+        if regname.startswith("full"):
+            res.append((regname, fspec))
+    for (regname, fspec) in fuspecs.items():
+        if not regname.startswith("full"):
+            res.append((regname, fspec))
+    return enumerate(res)
+
 
 class NonProductionCore(Elaboratable):
     def __init__(self):
@@ -111,7 +122,8 @@ class NonProductionCore(Elaboratable):
             rdpickers[regfile] = {}
 
             # for each named regfile port, connect up all FUs to that port
-            for rpidx, (regname, fspec) in enumerate(fuspecs.items()):
+            for rpidx, (regname, fspec) in sort_fuspecs(fuspecs):
+                print ("connect rd", rpidx, regname, fspec)
                 # get the regfile specs for this regfile port
                 (rf, read, write, wid, fuspec) = fspec
                 name = "rdflag_%s_%s" % (regfile, regname)
@@ -119,14 +131,19 @@ class NonProductionCore(Elaboratable):
                 comb += rdflag.eq(rf)
 
                 # "munge" the regfile port index, due to full-port access
-                if regfile in ['XER', 'CA']:
+                if regfile == 'XER':
                     if regname.startswith('full'):
-                        rpidx = 0 # by convention, first port
+                        rpidx == 0 # by convention, first port
                     else:
                         rpidx += 1 # start indexing port 0 from 1
+                if regfile in 'CR':
+                    if regname.startswith('full'):
+                        assert rpidx == 0 # by convention, first port
+                    else:
+                        assert rpidx >= 1 # start indexing port 0 from 1
 
                 # select the required read port.  these are pre-defined sizes
-                print (regfile, regs.rf.keys())
+                print (rpidx, regfile, regs.rf.keys())
                 rport = regs.rf[regfile.lower()].r_ports[rpidx]
 
                 # create a priority picker to manage this port
@@ -177,16 +194,22 @@ class NonProductionCore(Elaboratable):
         for regfile, spec in byregfiles_wr.items():
             fuspecs = byregfiles_wrspec[regfile]
             wrpickers[regfile] = {}
-            for rpidx, (regname, fspec) in enumerate(fuspecs.items()):
+            for rpidx, (regname, fspec) in sort_fuspecs(fuspecs):
+                print ("connect wr", rpidx, regname, fspec)
                 # get the regfile specs for this regfile port
                 (rf, read, write, wid, fuspec) = fspec
 
                 # "munge" the regfile port index, due to full-port access
-                if regfile in ['XER', 'CA']:
+                if regfile == 'XER':
                     if regname.startswith('full'):
-                        rpidx = 0 # by convention, first port
+                        rpidx == 0 # by convention, first port
                     else:
                         rpidx += 1 # start indexing port 0 from 1
+                if regfile == 'CR':
+                    if regname.startswith('full'):
+                        assert rpidx == 0 # by convention, first port
+                    else:
+                        assert rpidx >= 1 # start indexing port 0 from 1
 
                 # select the required write port.  these are pre-defined sizes
                 print (regfile, regs.rf.keys())