From: Luke Kenneth Casson Leighton Date: Fri, 9 Nov 2018 09:54:23 +0000 (+0000) Subject: elwidth version of lt X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2a993d7eca977865b28725136075d05759d29044;p=riscv-isa-sim.git elwidth version of lt --- diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc index 03ffe7f..261adb8 100644 --- a/riscv/sv_insn_redirect.cc +++ b/riscv/sv_insn_redirect.cc @@ -754,7 +754,19 @@ bool sv_proc_t::rv_lt(sv_reg_t const & lhs, sv_reg_t const & rhs) bool sv_proc_t::rv_lt(sv_sreg_t const & lhs, sv_sreg_t const & rhs) { - return lhs < rhs; + uint8_t bitwidth = _insn->src_bitwidth; + int64_t vlhs = 0; + int64_t vrhs = 0; + if (rv_int_op_prepare(lhs, rhs, vlhs, vrhs, bitwidth)) { + bool result = lhs < rhs; + fprintf(stderr, "lt result %lx %lx %x\n", + (int64_t)lhs, (int64_t)rhs, result); + return result; + } + bool result = vlhs < vrhs; + fprintf(stderr, "lt result %lx %lx %d bw %d\n", + (int64_t)lhs, (int64_t)rhs, result, bitwidth); + return result; } bool sv_proc_t::rv_gt(sv_reg_t const & lhs, sv_reg_t const & rhs)