From: Anton Blanchard Date: Tue, 19 May 2020 01:22:29 +0000 (+1000) Subject: Fix yosys build after MMU merge X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2aae3bf7a4bceda6b62cdc3c591ba3f31b52a961;p=microwatt.git Fix yosys build after MMU merge Signed-off-by: Anton Blanchard --- diff --git a/Makefile.synth b/Makefile.synth index 87f02fc..b0fb274 100644 --- a/Makefile.synth +++ b/Makefile.synth @@ -45,7 +45,7 @@ OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg VHDL_FILES = fpga/soc_reset.vhdl fpga/clk_gen_bypass.vhd decode_types.vhdl VHDL_FILES += common.vhdl wishbone_types.vhdl wishbone_debug_master.vhdl VHDL_FILES += wishbone_arbiter.vhdl cache_ram.vhdl utils.vhdl plru.vhdl -VHDL_FILES += helpers.vhdl dcache.vhdl core_debug.vhdl fetch1.vhdl fetch2.vhdl +VHDL_FILES += helpers.vhdl mmu.vhdl dcache.vhdl core_debug.vhdl fetch1.vhdl fetch2.vhdl VHDL_FILES += register_file.vhdl insn_helpers.vhdl multiply.vhdl divider.vhdl VHDL_FILES += logical.vhdl crhelpers.vhdl countzero.vhdl rotator.vhdl VHDL_FILES += ppc_fx_insns.vhdl execute1.vhdl decode1.vhdl cr_file.vhdl