From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sun, 26 Aug 2012 22:44:26 +0000 (+0200)
Subject: add tb_RecorderCsr.py
X-Git-Tag: 24jan2021_ls180~2575^2~163
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2abd7f664dbd3f96263269621f63eb075081640c;p=litex.git

add tb_RecorderCsr.py
fixs in recorder.py
---

diff --git a/migScope/recorder.py b/migScope/recorder.py
index d8f654b3..1e53733c 100644
--- a/migScope/recorder.py
+++ b/migScope/recorder.py
@@ -49,13 +49,11 @@ class Storage:
 			).Elif(self.start,
 				self._put_cnt.eq(0),
 				self._get_cnt.eq(0),
-				self._get_ptr.eq(self._put_ptr-size_minus_offset)
-			),
-			If(self.put,
+				self._get_ptr.eq(self._put_ptr-self.offset)
+			).Elif(self.put & ~self.done,
 				self._put_cnt.eq(self._put_cnt+1),
 				self._put_ptr.eq(self._put_ptr+1)
-			),
-			If(self.get,
+			).Elif(self.get,
 				self._get_cnt.eq(self._get_cnt+1),
 				self._get_ptr.eq(self._get_ptr+1)
 			)
@@ -83,6 +81,7 @@ class Sequencer:
 		self.ctl_done = Signal()
 		# Triggers interface
 		self.trig_hit  = Signal()
+		self._trig_hit_d = Signal()
 		# Recorder interface
 		self.rec_offset = Signal(BV(self.depth_width))
 		self.rec_size = Signal(BV(self.depth_width))
@@ -104,10 +103,11 @@ class Sequencer:
 				self.enable.eq(0)
 			)
 			]
+		sync += [self._trig_hit_d.eq(self.trig_hit)]
 		comb += [
 			self.rec_offset.eq(self.ctl_offset),
 			self.rec_size.eq(self.ctl_size),
-			self.rec_start.eq(self.enable & self.trig_hit),
+			self.rec_start.eq(self.enable & (self.trig_hit & ~self._trig_hit_d)),
 			self.ctl_done.eq(~self.enable)
 			]
 		return Fragment(comb=comb, sync=sync)
@@ -130,7 +130,7 @@ class Recorder:
 		self._size = RegisterField("size", self.depth_width, reset=1)
 		self._offset = RegisterField("offset", self.depth_width, reset=1)
 		
-		self._get = RegisterField("get", reset=1)
+		self._get = RegisterField("get", reset=0)
 		self._get_dat = RegisterField("get_dat", self.width, reset=1,access_bus=READ_ONLY, access_dev=WRITE_ONLY)
 		
 		regs = [self._rst, self._arm, self._done,
@@ -153,7 +153,9 @@ class Recorder:
 			self.sequencer.ctl_offset.eq(self._offset.field.r),
 			self.sequencer.ctl_size.eq(self._size.field.r),
 			self.sequencer.ctl_arm.eq(self._arm.field.r),
-			self._done.field.w.eq(self.sequencer.ctl_done)
+			self._done.field.w.eq(self.sequencer.ctl_done),
+			self.storage.get.eq(self._get.field.r),
+			self._get_dat.field.w.eq(self.storage.get_dat)
 			]
 		
 		#Storage <--> Sequencer <--> Trigger
@@ -170,4 +172,4 @@ class Recorder:
 
 		return self.bank.get_fragment()+\
 			self.storage.get_fragment()+self.sequencer.get_fragment()+\
-			Fragment(comb=comb, sync=sync)
\ No newline at end of file
+			Fragment(comb=comb, sync=sync)
diff --git a/sim/tb_RecorderCsr.py b/sim/tb_RecorderCsr.py
new file mode 100644
index 00000000..1fa6b8bf
--- /dev/null
+++ b/sim/tb_RecorderCsr.py
@@ -0,0 +1,107 @@
+from migen.fhdl.structure import *
+from migen.fhdl import verilog, autofragment
+from migen.bus import csr
+from migen.sim.generic import Simulator, PureSimulable, TopLevel
+from migen.sim.icarus import Runner
+from migen.bus.transactions import *
+
+import sys
+sys.path.append("../")
+
+from migScope import recorder
+
+
+arm_done = False
+trig_dat = 0
+
+rec_done = False
+
+dat_rdy = False
+
+def csr_transactions():
+
+	#Reset
+	yield TWrite(0, 1)
+	yield TWrite(0, 0)
+	
+	#Size
+	yield TWrite(3, 0)
+	yield TWrite(4, 32)
+	
+	#Offset
+	yield TWrite(5, 0)
+	yield TWrite(6, 0)
+	
+	#Arm
+	yield TWrite(1, 1)
+	
+	for t in range(10):
+		yield None
+		
+	global arm_done
+	arm_done = True
+	
+	global rec_done
+	while not rec_done:
+		yield None
+
+	global dat_rdy	
+	for t in range(32):
+		yield TWrite(7, 1)
+		dat_rdy = False
+		yield TWrite(7, 0)
+		yield TRead(8)
+		yield TRead(9)
+		yield TRead(10)
+		yield TRead(11)
+		dat_rdy = True
+
+	dat_rdy = False
+
+	for t in range(100):
+		yield None
+
+def main():
+	# Csr Master
+	csr_master0 = csr.Initiator(csr_transactions())
+
+	# Recorder
+	recorder0 = recorder.Recorder(0,32,1024)
+	
+	# Csr Interconnect
+	csrcon0 = csr.Interconnect(csr_master0.bus, 
+			[
+				recorder0.bank.interface
+			])
+
+	# Recorder Data
+	def recorder_data(s):
+		global arm_done
+		if arm_done:
+			s.wr(recorder0.trig_hit,1)
+			arm_done = False
+
+		global trig_dat
+		s.wr(recorder0.trig_dat,trig_dat)
+		trig_dat += 1
+			
+		global rec_done
+		if s.rd(recorder0.sequencer.rec_done) == 1:
+			rec_done = True
+		
+		if dat_rdy:
+			print("%08X" %s.rd(recorder0._get_dat.field.w))
+		
+
+	# Simulation
+	def end_simulation(s):
+		s.interrupt = csr_master0.done
+
+	fragment = autofragment.from_local()
+	fragment += Fragment(sim=[end_simulation])
+	fragment += Fragment(sim=[recorder_data])
+	sim = Simulator(fragment, Runner(),TopLevel("tb_RecorderCsr.vcd"))
+	sim.run(10000)
+
+main()
+input()
\ No newline at end of file