From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 27 Jul 2018 09:49:59 +0000 (+0100)
Subject: add extra -D options to makefile template
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2ac4991945acb14b1d4d5d7b79fba196d3618d40;p=pinmux.git

add extra -D options to makefile template
---

diff --git a/src/bsv/Makefile.template b/src/bsv/Makefile.template
index bd81d52..5d2e955 100644
--- a/src/bsv/Makefile.template
+++ b/src/bsv/Makefile.template
@@ -49,7 +49,18 @@ gen_verilog: check-restore check-blue
 	@echo Compiling mkTbSoc in Verilog for simulations ...
 	@mkdir -p $(BSVBUILDDIR); 
 	@mkdir -p $(VERILOGDIR); 
-	bsc -u -verilog -elab -vdir $(VERILOGDIR) -bdir $(BSVBUILDDIR) -info-dir $(BSVBUILDDIR) $(define_macros) -D verilog=True $(BSVCOMPILEOPTS) -verilog-filter ${BLUESPECDIR}/bin/basicinout -p $(BSVINCDIR) -g $(TOP_MODULE) $(TOP_DIR)/$(TOP_FILE) 2>&1 | tee bsv_compile.log
+	bsc -u -verilog -elab -vdir $(VERILOGDIR) -bdir $(BSVBUILDDIR) \
+	        -info-dir $(BSVBUILDDIR) $(define_macros) \
+	        -D RV64=True -D muldiv=True -D sequential=True \
+	        -D atomic=True -D spfpu=True -D dpfpu=True \
+	        -D bpu=True -D MMU=True -D perf=True \
+	        -D prefetch=True -D CLINT=True \
+	        -D      simulate=True -D SDRAM=True \
+	        -D GPIO_MUX=True \
+	        -D verilog=True $(BSVCOMPILEOPTS) -verilog-filter \
+	        ${BLUESPECDIR}/bin/basicinout -p $(BSVINCDIR) \
+	        -g $(TOP_MODULE) $(TOP_DIR)/$(TOP_FILE) \
+	        2>&1 | tee bsv_compile.log
 	@echo Compilation finished
 
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