From: Florent Kermarrec Date: Wed, 12 Dec 2018 08:38:53 +0000 (+0100) Subject: soc/cores/cpu/vexriscv: update submodule X-Git-Tag: 24jan2021_ls180~1442 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2ace45e6f8916c7475d9e47e3e50331b2a7be09f;p=litex.git soc/cores/cpu/vexriscv: update submodule --- diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog index 395c5ee2..d7bbc2c1 160000 --- a/litex/soc/cores/cpu/vexriscv/verilog +++ b/litex/soc/cores/cpu/vexriscv/verilog @@ -1 +1 @@ -Subproject commit 395c5ee2868ffbe36db290a4a4ec0eabc0f5c2b5 +Subproject commit d7bbc2c167f1a0886c446d3c305d0ed4388570be diff --git a/litex/soc/software/include/base/csr-defs.h b/litex/soc/software/include/base/csr-defs.h index 5f5ea847..d98e8dfb 100644 --- a/litex/soc/software/include/base/csr-defs.h +++ b/litex/soc/software/include/base/csr-defs.h @@ -3,8 +3,8 @@ #define CSR_MSTATUS_MIE 0x8 -#define CSR_IRQ_MASK 0x330 -#define CSR_IRQ_PENDING 0x360 +#define CSR_IRQ_MASK 0xBC0 +#define CSR_IRQ_PENDING 0xFC0 #define CSR_DCACHE_INFO 0xCC0