From: Andrew Waterman Date: Mon, 26 Oct 2015 20:07:30 +0000 (-0700) Subject: Fix histogram for RVC X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2ace4c98e65e72444a9017fa4f568fe9858addbe;p=riscv-isa-sim.git Fix histogram for RVC No need to right-shift PC by 2. It's a map, so this is a false economy. --- diff --git a/riscv/execute.cc b/riscv/execute.cc index 249d6ae..4711b49 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -32,11 +32,10 @@ static void commit_log_print_insn(state_t* state, reg_t pc, insn_t insn) #endif } -inline void processor_t::update_histogram(size_t pc) +inline void processor_t::update_histogram(reg_t pc) { #ifdef RISCV_ENABLE_HISTOGRAM - size_t idx = pc >> 2; - pc_histogram[idx]++; + pc_histogram[pc]++; #endif } diff --git a/riscv/processor.cc b/riscv/processor.cc index 8870cc9..37b77c5 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -38,10 +38,9 @@ processor_t::~processor_t() #ifdef RISCV_ENABLE_HISTOGRAM if (histogram_enabled) { - fprintf(stderr, "PC Histogram size:%lu\n", pc_histogram.size()); - for(auto iterator = pc_histogram.begin(); iterator != pc_histogram.end(); ++iterator) { - fprintf(stderr, "%0lx %lu\n", (iterator->first << 2), iterator->second); - } + fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size()); + for (auto it : pc_histogram) + fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second); } #endif diff --git a/riscv/processor.h b/riscv/processor.h index f1de05e..fe0a121 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -96,7 +96,7 @@ public: void push_privilege_stack(); void pop_privilege_stack(); void yield_load_reservation() { state.load_reservation = (reg_t)-1; } - void update_histogram(size_t pc); + void update_histogram(reg_t pc); void register_insn(insn_desc_t); void register_extension(extension_t*); @@ -116,7 +116,7 @@ private: bool histogram_enabled; std::vector instructions; - std::map pc_histogram; + std::map pc_histogram; static const size_t OPCODE_CACHE_SIZE = 8191; insn_desc_t opcode_cache[OPCODE_CACHE_SIZE];