From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Wed, 27 Sep 2023 07:35:17 +0000 (+0100)
Subject: Added english language description and brackets for ldbrx instruction
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2acf422974ac707df9de1c7d8bae0e463fdc4e91;p=openpower-isa.git

Added english language description and brackets for ldbrx instruction
---

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 337e7c53..233b45ed 100644
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -720,6 +720,22 @@ Pseudo-code:
         || load_data[24:31] || load_data[16:23]
         || load_data[8:15]  || load_data[0:7])
 
+Description:
+
+    Let the effective address (EA) be the sum (RA|0)+(RB).
+    Bits 0:7 of the doubleword in storage addressed by EA
+    are loaded into RT[56:63] . Bits 8:15 of the doubleword in
+    storage addressed by EA are loaded into RT[48:55] . Bits
+    16:23 of the doubleword in storage addressed by EA
+    are loaded into RT[40:47]. Bits 24:31 of the doubleword in
+    storage addressed by EA are loaded into RT 32:39 . Bits
+    32:39 of the doubleword in storage addressed by EA
+    are loaded into RT[24:31]. Bits 40:47 of the doubleword in
+    storage addressed by EA are loaded into RT[16:23] . Bits
+    48:55 of the doubleword in storage addressed by EA
+    are loaded into RT[8:15] . Bits 56:63 of the doubleword in
+    storage addressed by EA are loaded into RT[0:7] .
+
 Special Registers Altered:
 
     None