From: Ali Saidi <saidi@eecs.umich.edu>
Date: Wed, 29 Mar 2006 23:42:53 +0000 (-0500)
Subject: page_table.cc is a syscall only kinda thing
X-Git-Tag: m5_2.0_beta1~137^2~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2ad1db3fde4f95eaf0b1be77910de0feb2185712;p=gem5.git

page_table.cc is a syscall only kinda thing
fix tlbs for newmem

SConscript:
    page_table.cc is a syscall only kinda thing
arch/alpha/tlb.cc:
arch/alpha/tlb.hh:
    fix tlbs for newmem

--HG--
extra : convert_revision : 0aafcb9698b993a807be883bde1696ee4d33b408
---

diff --git a/SConscript b/SConscript
index 008c794e3..daca62c06 100644
--- a/SConscript
+++ b/SConscript
@@ -90,7 +90,6 @@ base_sources = Split('''
 
         mem/connector.cc
         mem/mem_object.cc
-        mem/page_table.cc
         mem/physical.cc
         mem/port.cc
         mem/translating_port.cc
@@ -255,6 +254,7 @@ turbolaser_sources = Split('''
 # Syscall emulation (non-full-system) sources
 syscall_emulation_sources = Split('''
         kern/linux/linux.cc
+        mem/page_table.cc
 	sim/process.cc
 	sim/syscall_emul.cc
         ''')
diff --git a/arch/alpha/tlb.cc b/arch/alpha/tlb.cc
index 562235ef8..3f991b10c 100644
--- a/arch/alpha/tlb.cc
+++ b/arch/alpha/tlb.cc
@@ -94,7 +94,7 @@ AlphaTLB::lookup(Addr vpn, uint8_t asn) const
 
 
 void
-AlphaTLB::checkCacheability(MemReqPtr &req)
+AlphaTLB::checkCacheability(CpuRequestPtr &req)
 {
     // in Alpha, cacheability is controlled by upper-level bits of the
     // physical address
@@ -292,7 +292,7 @@ AlphaITB::regStats()
 
 
 Fault
-AlphaITB::translate(MemReqPtr &req) const
+AlphaITB::translate(CpuRequestPtr &req) const
 {
     ExecContext *xc = req->xc;
 
@@ -451,7 +451,7 @@ AlphaDTB::regStats()
 }
 
 Fault
-AlphaDTB::translate(MemReqPtr &req, bool write) const
+AlphaDTB::translate(CpuRequestPtr &req, bool write) const
 {
     ExecContext *xc = req->xc;
     Addr pc = xc->readPC();
diff --git a/arch/alpha/tlb.hh b/arch/alpha/tlb.hh
index 676345f01..fe156b7e3 100644
--- a/arch/alpha/tlb.hh
+++ b/arch/alpha/tlb.hh
@@ -35,7 +35,7 @@
 #include "arch/alpha/isa_traits.hh"
 #include "arch/alpha/faults.hh"
 #include "base/statistics.hh"
-#include "mem/mem_req.hh"
+#include "mem/request.hh"
 #include "sim/sim_object.hh"
 
 class ExecContext;
@@ -73,7 +73,7 @@ class AlphaTLB : public SimObject
         return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
     }
 
-    static void checkCacheability(MemReqPtr &req);
+    static void checkCacheability(CpuRequestPtr &req);
 
     // Checkpointing
     virtual void serialize(std::ostream &os);
@@ -92,7 +92,7 @@ class AlphaITB : public AlphaTLB
     AlphaITB(const std::string &name, int size);
     virtual void regStats();
 
-    Fault translate(MemReqPtr &req) const;
+    Fault translate(CpuRequestPtr &req) const;
 };
 
 class AlphaDTB : public AlphaTLB
@@ -115,7 +115,7 @@ class AlphaDTB : public AlphaTLB
     AlphaDTB(const std::string &name, int size);
     virtual void regStats();
 
-    Fault translate(MemReqPtr &req, bool write) const;
+    Fault translate(CpuRequestPtr &req, bool write) const;
 };
 
 #endif // __ALPHA_MEMORY_HH__