From: Tobias Platen <tplaten@posteo.de>
Date: Fri, 14 Feb 2020 16:30:44 +0000 (+0100)
Subject: first example code
X-Git-Tag: partial-core-ls180-gdsii~249
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2ad689cc8177c6c7340f72c171960c8d4ab903a3;p=soclayout.git

first example code
---

diff --git a/coriolis2/__init__.py b/coriolis2/__init__.py
new file mode 100644
index 0000000..e69de29
diff --git a/coriolis2/katana.py b/coriolis2/katana.py
new file mode 100644
index 0000000..442b2fc
--- /dev/null
+++ b/coriolis2/katana.py
@@ -0,0 +1,12 @@
+
+from Hurricane import DebugSession
+
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n543' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'dl(6)' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'n0_dl_7_0_6' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n822' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n734' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n1386' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n763' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n800' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12491_n428_1' ) )
diff --git a/coriolis2/settings.py b/coriolis2/settings.py
new file mode 100644
index 0000000..a22a9ea
--- /dev/null
+++ b/coriolis2/settings.py
@@ -0,0 +1,37 @@
+# -*- Mode:Python -*-
+
+import Cfg
+import Viewer
+import symbolic.cmos
+from   helpers       import l, u, n
+
+
+Cfg.Configuration.pushDefaultPriority( Cfg.Parameter.Priority.UserFile )
+
+
+Viewer.Graphics.setStyle( 'Alliance.Classic [black]' )
+ 
+Cfg.getParamBool      ( 'misc.catchCore'              ).setBool      ( False   )
+Cfg.getParamBool      ( 'misc.info'                   ).setBool      ( False   )
+Cfg.getParamBool      ( 'misc.paranoid'               ).setBool      ( False   )
+Cfg.getParamBool      ( 'misc.bug'                    ).setBool      ( False   )
+Cfg.getParamBool      ( 'misc.logMode'                ).setBool      ( False   )
+Cfg.getParamBool      ( 'misc.verboseLevel1'          ).setBool      ( True    )
+Cfg.getParamBool      ( 'misc.verboseLevel2'          ).setBool      ( True    )
+#Cfg.getParamInt       ( 'misc.minTraceLevel'          ).setInt       ( 159     )
+#Cfg.getParamInt       ( 'misc.maxTraceLevel'          ).setInt       ( 160     )
+Cfg.getParamEnumerate ( 'etesian.effort'              ).setInt       ( 2       )
+Cfg.getParamPercentage( 'etesian.spaceMargin'         ).setPercentage( 5.0     )
+Cfg.getParamPercentage( 'etesian.aspectRatio'         ).setPercentage( 100.0   )
+Cfg.getParamBool      ( 'etesian.uniformDensity'      ).setBool      ( True    )
+Cfg.getParamInt       ( 'anabatic.edgeLenght'         ).setInt       ( 24      )
+Cfg.getParamInt       ( 'anabatic.edgeWidth'          ).setInt       ( 8       )
+Cfg.getParamString    ( 'anabatic.topRoutingLayer'    ).setString    ( 'METAL5')
+Cfg.getParamInt       ( 'katana.eventsLimit'          ).setInt       ( 1000000 )
+Cfg.getParamInt       ( 'katana.hTracksReservedLocal' ).setInt       ( 7       )
+Cfg.getParamInt       ( 'katana.vTracksReservedLocal' ).setInt       ( 6       )
+#Cfg.getParamInt       ( 'clockTree.minimumSide'       ).setInt       ( l(1000) )
+
+Cfg.Configuration.popDefaultPriority()
+
+print 'Successfully read user configuration'
diff --git a/examples/part_sig_add.py b/examples/part_sig_add.py
new file mode 100644
index 0000000..5a868b4
--- /dev/null
+++ b/examples/part_sig_add.py
@@ -0,0 +1,42 @@
+from nmigen.cli import rtlil
+from ieee754.part.test.test_partsig import TestAddMod
+import subprocess
+import os
+from nmigen import Signal
+
+def test():
+    width = 16
+    part_mask = Signal(4)  # divide into 4-bits
+    module = TestAddMod(width, part_mask)
+    sim = create_ilang(module,
+                               [part_mask,
+                                module.a.sig,
+                                module.b.sig,
+                                module.add_output,
+                                module.eq_output],
+                               "top")
+                            
+def run_yosys(test_name):
+    liberty_file = os.getenv("HOME")+"/coriolis-2.x/src/alliance-check-toolkit/cells/nsxlib/nsxlib.lib"
+    print("test_name:",test_name)
+    cmd = [
+        "read_ilang top.il",
+        "hierarchy -check -top top",
+        "synth -top top",
+        "dfflibmap -liberty "+liberty_file,
+        "abc -liberty "+liberty_file,
+        "clean",
+        "write_blif test.blif"
+    ]
+    cmd = "; ".join(cmd)
+    subprocess.call(["yosys","-p",cmd])
+
+def create_ilang(dut, ports, test_name):
+    vl = rtlil.convert(dut, name=test_name, ports=ports)
+    with open("%s.il" % test_name, "w") as f:
+        f.write(vl)
+    run_yosys(test_name)
+
+
+if __name__ == "__main__":
+    test()