From: Ben Skeggs <bskeggs@redhat.com>
Date: Sun, 7 Jun 2020 22:43:54 +0000 (+1000)
Subject: nvir/nir: flesh out options
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2ad6f1b7bb85798b0a0647b27c6b17a575d82fa3;p=mesa.git

nvir/nir: flesh out options

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
---

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index d82c1ab442c..590f67493f3 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
@@ -3298,16 +3298,19 @@ nvir_nir_shader_compiler_options(int chipset)
       .lower_fdiv = false,
       .lower_ffma = false,
       .fuse_ffma = false, /* nir doesn't track mad vs fma */
+      .lower_flrp16 = false,
       .lower_flrp32 = true,
       .lower_flrp64 = true,
       .lower_fpow = false,
       .lower_fsat = false,
       .lower_fsqrt = false, // TODO: only before gm200
+      .lower_sincos = false,
       .lower_fmod = true,
       .lower_bitfield_extract = false,
       .lower_bitfield_extract_to_shifts = false,
       .lower_bitfield_insert = false,
       .lower_bitfield_insert_to_shifts = false,
+      .lower_bitfield_insert_to_bitfield_select = false,
       .lower_bitfield_reverse = false,
       .lower_bit_count = false,
       .lower_ifind_msb = false,
@@ -3318,12 +3321,18 @@ nvir_nir_shader_compiler_options(int chipset)
       .lower_negate = false,
       .lower_sub = true,
       .lower_scmp = true, // TODO: not implemented yet
+      .lower_vector_cmp = false,
       .lower_idiv = true,
+      .lower_bitops = false,
       .lower_isign = false, // TODO
+      .lower_fsign = false,
+      .lower_fdph = false,
+      .lower_fdot = false,
       .fdot_replicates = false, // TODO
       .lower_ffloor = false, // TODO
       .lower_ffract = true,
       .lower_fceil = false, // TODO
+      .lower_ftrunc = false,
       .lower_ldexp = true,
       .lower_pack_half_2x16 = true,
       .lower_pack_unorm_2x16 = true,
@@ -3335,21 +3344,29 @@ nvir_nir_shader_compiler_options(int chipset)
       .lower_unpack_snorm_2x16 = true,
       .lower_unpack_unorm_4x8 = true,
       .lower_unpack_snorm_4x8 = true,
+      .lower_pack_split = false,
       .lower_extract_byte = true,
       .lower_extract_word = true,
       .lower_all_io_to_temps = false,
+      .lower_all_io_to_elements = false,
       .vertex_id_zero_based = false,
       .lower_base_vertex = false,
       .lower_helper_invocation = false,
+      .optimize_sample_mask_in = false,
       .lower_cs_local_index_from_id = true,
       .lower_cs_local_id_from_index = false,
       .lower_device_index_to_zero = false, // TODO
       .lower_wpos_pntc = false, // TODO
       .lower_hadd = true, // TODO
       .lower_add_sat = true, // TODO
+      .vectorize_io = false,
       .lower_to_scalar = true,
+      .unify_interfaces = false,
       .use_interpolated_input_intrinsics = true,
       .lower_mul_2x32_64 = true, // TODO
+      .lower_rotate = false,
+      .has_imul24 = false,
+      .intel_vec4 = false,
       .max_unroll_iterations = 32,
       .lower_int64_options = (nir_lower_int64_options) ( // TODO
             nir_lower_divmod64 |