From: lkcl <lkcl@web>
Date: Sat, 30 Jan 2021 00:21:30 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~244
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2adc527ad0fee4f3d1fe00b9d486f1a4101a4068;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index e60c5bb85..15ac7b3df 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -16,10 +16,10 @@ Links:
 * <https://bugs.libre-soc.org/show_bug.cgi?id=241> gem5 / ISACaller simulator
   - <https://bugs.libre-soc.org/show_bug.cgi?id=581> gem5 upstreaming
 * <https://bugs.libre-soc.org/show_bug.cgi?id=583> TestIssuer
+* <https://bugs.libre-soc.org/show_bug.cgi?id=588> PowerDecoder2
 * <https://bugs.libre-soc.org/show_bug.cgi?id=587> setvl ancillary tasks
  (instruction form SVL-Form, field designations, pseudocode, SPR allocation)
 
-
 # Code to convert
 
 There are four projects: