From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 29 Oct 2018 09:54:21 +0000 (+0000)
Subject: add redirector operators for sv_freg_t to uint32 and uint64
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2adc7cbb29ed03d794f3d9e63de6b01fb1977518;p=riscv-isa-sim.git

add redirector operators for sv_freg_t to uint32 and uint64
---

diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h
index 37fca6a..0b70997 100644
--- a/riscv/insns/fsw.h
+++ b/riscv/insns/fsw.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-MMU.store_uint32(insn.rs1(), insn.s_imm(), ((freg_t)FRS2).v[0]); // RS1
+MMU.store_uint32(insn.rs1(), insn.s_imm(), FRS2.to_uint32()); // RS1
diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 3eb7a39..a5d9942 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -885,3 +885,13 @@ void sv_proc_t::mmu_store(reg_spec_t const& spec, sv_reg_t const& offs,
     }
 }
 
+uint64_t sv_freg_t::to_uint64() const&
+{
+    return reg.v[0];
+}
+
+uint32_t sv_freg_t::to_uint32() const&
+{
+    return reg.v[0];
+}
+
diff --git a/riscv/sv_reg.h b/riscv/sv_reg.h
index 37d6354..0fc1fb0 100644
--- a/riscv/sv_reg.h
+++ b/riscv/sv_reg.h
@@ -84,11 +84,14 @@ public:
     sv_freg_t(freg_t _reg, int xlen, uint8_t _elwidth) :
                 sv_regbase_t(xlen, _elwidth), reg(_reg)
                                                 {}
-
     freg_t reg;
 public:
 
   operator freg_t() const& { return reg; }
+
+  uint64_t to_uint64() const&;
+  uint32_t to_uint32() const&;
+
 };
 
 class sv_float32_t : public sv_regbase_t {